Abstract: In a logarithmic amplifier circuit including a plurality of cascaded differential amplifiers, a plurality of blocks of logarithmic full-wave rectifiers are provided, each producing output currents having logarithmic full-wave rectification characteristics in respect to voltages of their input signals. Each logarithmic full-wave rectifier is formed by a plurality of squaring full-wave rectifiers each producing an intermediate current having squaring full-wave characteristics. A current adder is provided for each or a group of the squaring full-wave rectifiers to add up the intermediate currents thereof and produce an output current. A common adder is provided for adding the output currents from all logarithmic full-wave rectifiers to produce a current output signal.

Abstract: A four-quadrant analog multiplier circuit provides an output which is protional to two voltage inputs that each represent a multiplicand. In a first embodiment, the circuit comprises a complementary pair of field effect transistors having gain constants equal in magnitude and in which the p-channel threshold voltage is larger than the n- channel threshold voltage. The gates of the transistors are coupled in common. One input is added to a bias voltage and the voltage sum is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors, while the remaining source/drain terminals are coupled in common to provide an output node. A second embodiment of the invention is composed of two circuits as described above, where the polarities of the inputs to one pair of transistors are reversed relative to those of the second pair, and the output nodes of the individual pairs are coupled together.