Abstract: A method and apparatus for encoding MATCH signal and MATCH ADDRESS signal generation for a content addressable memory ("CAM") array is disclosed. Each CAM core has an output encoder for providing a MATCH signal and, if a MATCH is determined, a MATCH.sub.-- ADDRESS signal indicative of the location in the CAM of the data of interest. In order to speed the critical search path, each signal line for the MATCH and MATCH.sub.-- ADDRESS have the same number of transistors, with designated MATCH.sub.-- ADDRESS transistors being used to indicate a MATCH, that is, providing a substitute MATCH signal, if the MATCH line has no transistor. The output encoder output signals are encoded to provide a final MATCH signal and a final MATCH.sub.-- ADDRESS which adds a CAM core designator to the MATCH.sub.-- ADDRESS from the CAM core having the data.

Abstract: A circuit interrupter including an improved arc detection system which trips the interrupter in response to currents having frequencies and/or characteristics associated with arcing within the associated alternating current electrical system. The arc monitoring circuit determines if the signal produced by a current transducer is the result of arcing. The arc detection system includes two swept filters and associated amplifiers which produce a signal which has an amplitude representative of the frequencies present in the alternating current of the electric system. The portion of the filtered signal which has amplitudes above a predetermined level is integrated to produce a trip signal for the circuit interrupter when the value of the integration exceeds a predetermined limit.

Abstract: A recording medium for a computer contains sectors, each of which represents a section of data that has originally been supplied by a user. As the user data is sent to the recording medium from the memory of the computer, an adjust bit determining circuit determines the adjust bit for a block of the write data. The adjust bit-value is such that the sum of the DC levels for the write data at a given point is equal to zero or approaches zero. The user data is converted using RLL(1,7) codes and PWM is performed to derive the write data. The circuit includes an encoder for receiving the user data two bits at a time. The encoder outputs DSV values for the 2-bit user data. A first circuit group for accumulating the DSV values from the encoder is used acquire block DSV values of data belonging to the plurality of blocks of the data section. A second circuit group accumulates these block DSV values computed by the first circuit group and calculates a temporary sector DSV value.

Abstract: An analog memory unit that can be implemented, at least in part, on an application specific integrated circuit (ASIC), utilizes at least the ASIC arithmetic logic unit (ALU) to enhance performance and to generate and store an accurate measure of power line thermal status. The memory unit includes an analog-to-digital (A/D) converter for converting an input analog signal from a parallel R-C circuit to a digital signal and a scaler for scaling the digital signal from the A/D converter to within a range acceptable for further processing. The memory unit also includes an arithmetic logic unit (ALU) which receives input signals from the scaler and from a digital thermal memory. The input signal supplied to the ALU from the digital thermal memory is a four bit (digital) value proportional to the measured actual thermal status of the subject power line. The output of the ALU is connected to the input of latches which latch, or store, the digital signal produced by the ALU.

Abstract: A decoding device is provided including a code FIFO memory unit for sequentially storing a bit stream, a barrel shifter for shifting and then outputting codes properly, an accumulator for computing the shift amount of the barrel shifter and issuing a request to read data to the code FIFO memory unit, a DCT coefficient decoder for decoding DCT coefficients, a variable-length code decoder for decoding variable-length codes other than DCT coefficients, a fixed-length code decoder for decoding fixed-length codes, a register unit for storing decoded data, a decoding controller for controlling the decoders in accordance with the decoded data stored in the register unit and decoded data output by the decoders and a memory controller for controlling operations to store DCT coefficients in a memory unit A.

Abstract: A high performance variable length decoder which includes a tagging circuit that tags the boundaries of code words in an incoming bit stream, providing a tag stream output and a bussed bit stream output that coincides in time with the tag stream output. The bussed tag stream output is connected to an input of a high speed parallel word length computation circuit, and the bussed bit stream output is connected to an input of a parallel value decoder circuit. The parallel word length computation circuit (word length decoding loop) receives the bussed tag stream and computes (decodes) the length of a singular code word in a singular mode of operation, or the lengths of one or more contiguous code words in a contiguous mode of operation.

Abstract: A 16-bit data block is partitioned into upper 5-bit and 3-bit sub-blocks and lower 5-bit and 3-bit sub-blocks. During a single clock cycle, a first 5B/6B encoder portion encodes the upper 5-bit sub-block to produce an upper 6-bit sub-block, a first 3B/4B encoder portion encodes the upper 3-bit sub-block to produce an upper 4-bit sub-block, a second 5B/6B encoder portion encodes the lower 5-bit sub-block to produce a lower 6-bit sub-block, and a second 3B/4B encoder portion encodes the lower 3-bit sub-block to produce a lower 4-bit sub-block. During the same clock cycle, the running disparities of the upper 6-bit sub-block, the upper 4-bit sub-block and the lower 6-bit sub-block are simultaneously combinationally passed to the first 3B/4B encoder portion, the second 5B/6B encoder portion and the second 3B/4B encoder portion, respectively, to selectively complement the output sub-block to adjust running disparity.

Abstract: A discharge relay electrode is located between terminal electrodes of a gap-type surge absorber. In a microgap embodiment of the invention, a conducting film on a surface of an insulating tube is split by two circumferential gaps spaced apart longitudinally. The discharge relay electrode is positioned between the two gaps. In a gap type surge absorber, the discharge relay electrode is positioned within the insulating tube midway between the end electrodes, substantially filling the cross section of the tube, and dividing the interior of the tube into a plurality of chambers. For both types of surge absorbers, the discharge relay electrode is effective to relay discharge between the terminal electrodes.

Abstract: A system and method for reducing signal-to-noise ratio in a multi-component analog signal during analog to digital conversion. The multi-component analog signal is made up of a plurality of separate analog signals, with each of the separate analog signals having separate amplitude levels. A reference gain control signal, corresponding to the largest amplitude component of the multi-component signal, is first determined. Next, the reference gain control signal is used to generate a gain control signal. The gain control signal is then used to adjust each component of the multi-component signal by a gain value. Finally, the gain adjusted signals are converted to corresponding digital signals.

Abstract: An integrated circuit having a gate oxide, preferably for a DMOS circuit having a protective device against electrostatic overvoltages (ESD), is to connect a limiting circuit in series with the protective device. This series circuit means that, during the wafer production, an increased voltage can be applied to the gate of the integrated circuit, for testing the gate oxide, without the circuit being limited to a lower value. After testing, the limiting circuit is connected irreversibly in its low-resistance state, with the result that subsequent ESD interference voltages are limited by the built-in protective device. A zener zapping diode is provided as the limiting circuit. An advantageous result of the arrangement is the fact that an additional bonding connection for connecting the gate connection to the protective device is no longer necessary.

Abstract: An apparatus and method for parallel data compression and decompression uses packing and unpacking of data which has multi-variable components, for example, relational multi-variable content data such as tristimulus color space data used in color hard copy applications. Multiple input words are compressed in parallel compression engines and fed in parallel to a packer device which configures the codes in an order determined by order of compression and byte count for each word into a single bit string code. In the decompression cycle of the process, an unpacker device separates the single bit string code based upon length of a data string represented by a code word last decoded by either the decompression engine for that code word if the decompression engine is idle, or the length of the string that has been decoded so far if the decompression engine is currently working on a code.

Abstract: A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses.

Abstract: A variable length decoder with adaptive acceleration in processing of an encoded input bit stream which includes an input circuit for receiving the input bit stream and for providing a decoding window that includes a sequence of bits which include one or more code words to be decoded at an output thereof, a code word length decoding circuit for determining the combined length of a combination of two or more code words received from the input circuit in response to a first value of a control signal and for generating a combined length signal representative of the determined combined length, and for determining the length of an individual code word received from the input circuit in response to a second value of the control signal and for generating an individual word length signal representative of the determined length of the individual code word, a computation loop circuit for receiving the combined length signal or the individual word length signal from the code word length decoding circuit and, in response

Abstract: An analog/digital converter includes a comparator with two inputs and one output. One capacitor is connected between a reference potential and one of the inputs of the comparator. A coupling element is connected between a node point and the other of the inputs of the comparator. N further capacitors each have two terminals. One terminal of each of the further capacitors is connected to the node point. N individually controllable reversing switches each connect the other terminal of a respective one of the further capacitors to an input potential, a first reference potential or a second reference potential. A control device is connected to the output of the comparator and to the reversing switches to control the reversing switches for connecting at least some of the further capacitors to the input potential and for connecting each of the remainder of the further capacitors to one of the two reference potentials, during a transfer phase.

Abstract: A high-efficiency encoding apparatus having a data division circuit which applies 1-dimensional scanning to the orthogonal-transformed data obtained by applying orthogonal transformation to blocked digital data in the unit of block and divides the data into run-length data and coefficient data, an encoding circuit which applies run-length encoding to the divided run-length data by employing data of the highest probability of occurrence (for example 0), and an encoding circuit which applies run-length encoding to the divided coefficient data by employing data of the highest probability of occurrence (for example 1), thereby reduces the amount of the digital data.

Abstract: An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.

Abstract: A method of generating codes for error checking from a first and second types of data trains, first type of data trains having m symbols, second type of data trains having n symbols, m and n being natural numbers and m<n, comprising the steps of: generating n-m dummy data: and attaching the n-m dummy data to the first types of data train is disclosed.

Abstract: An integrated circuit system includes an integrated circuit with a heat sink assembly including a fusible core. In the event that power dissipation by the integrated circuit threatens to exceed its safe operating range, the fusible core melts, absorbing the heat of fusion and delaying further temperature increases. A motor is repeatedly activated to attempt to rotate a shaft within the fusible core. When the core is solid, the shaft cannot be turned, but once it melts the shaft turns. The shafts motion is detected and used to trigger a reduction in the drive clock frequency of the integrated circuit. This reduces power consumption and dissipation until the integrated circuit cools and the heat sink core solidifies.

Abstract: An analog to digital converter comprises: first to n.sup.th comparators, having a tandem structure, for comparing an input voltage signal with first to n.sup.th reference voltages and outputting first to n.sup.th bit outputs respectively, said n being a natural number more than one, said first comparator outputting a most significant bit of said first bit output; a first reference voltage generation circuit for generating said first reference voltage; second to n.sup.th reference voltage generation circuits for generating said second to n.sup.th reference voltages, p.sup.th reference voltages being generated in accordance with outputs of said first to (p-1).sup.th comparators, said p being a natural number and l<p<n.

Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.