Patents Examined by Tom Dickey
  • Patent number: 6989569
    Abstract: A MOS transistor with a controlled threshold voltage includes a SOI which includes a substrate composed of a semi-conducting material, a single crystal layer composed of a semi-conducting material and an insulating layer interposed between the substrate and the single crystal layer. The single crystal layer is formed therein with a source region, a drain region and a surrounded region surrounded by the source region and the drain region. The surrounded region includes a depletion layer having a composition surface which is in contact with the insulating layer. The MOS transistor comprises an EIB-MOS transistor of which the substrate is adapted to be applied with a voltage of a first polarity for inducing charges of a second polarity over the composition surface of the surrounded region.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: January 24, 2006
    Assignee: The University of Tokyo
    Inventors: Toshiro Hiramoto, Makoto Takamiya
  • Patent number: 6400003
    Abstract: In a field-effect semiconductor device, for example a power MOSFET, a body portion separates a channel-accommodating region from a drain region at a surface of a semiconductor body. This body portion includes a drift region which serves for current flow of charge carriers of a first conductivity type from the conduction channel to the drain region, in a conducting mode of the device. Instead of being a single region, the body portion also includes field-relief regions of the second conductivity type, which are depleted together with the drift region in a voltage blocking mode of the device to provide a voltage-carrying space-charge region. The drain region extends at least partially around the body portion at the surface, and the relief regions are located radially in this body portion.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: June 4, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Eddie Huang