Abstract: A method of fabricating bit lines is described. A semiconductor substrate has isolation structures formed therein. Gate structures are formed over the semiconductor substrate. Each gate structure comprises a conducting gate layer and a cap layer on the conducting gate layer. A common source and a drain is formed in the semiconductor substrate. A spacer is formed on the sidewall of each gate structure. A dielectric layer is formed over the semiconductor substrate. The dielectric layer is patterned to form bit line contact holes and bit line trenches, wherein the bit line contact holes expose the common sources, and the bit line trenches expose a part of the cap layer and a part of the isolation structures. The bit line contact holes and the bit line trenches are filled with a conducting layer; consequently, bit line contacts and patterned bit lines are formed.