Patents Examined by Ton Dunn
  • Patent number: 6409073
    Abstract: A substrate (10, 80) includes a conductive layer (16, 82) which is non-wettable by solder. A solder receiving stud (22, 84) is formed on the conductive layer, preferably by plating. If used for transferring solder, a solder bump (32) is selectively formed on the solder receiving stud since the surrounding conductive layer is not wettable by the solder. A receiving substrate, such as a semiconductor device (100), is aligned with the substrate. The solder bump is heated to a liquidus state and the solder bump makes physical contact with a solder accepting stud (120) of the receiving substrate. Because the area of the solder accepting stud is larger than the area of the corresponding stud on the transfer substrate, the majority of the solder will transfer to the receiving substrate upon separation. Alternatively, the device could itself already have bumps formed thereon, in which case an unbumped substrate is used to test the device, and solder remains on the device upon separation.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: June 25, 2002
    Assignee: Fraunhofer-Gesellschaft Zur Foerderung der Angewandten Forschung E.V.
    Inventors: Kenneth Kaskoun, Erik Jung, Werner Budweiser
  • Patent number: 6375063
    Abstract: A multi-step stud design and method for fabricating the same of special utility for producing closely packed interconnects in magnetic recording heads, particularly higher density magnetoresistive and giant magnetoresistive tape heads. The multi-step stud fabrication process and structure enables the achievement of significantly higher interconnect densities resulting in an increased number of channels per millimeter on a single computer mass storage device recording head. A resultant stronger encapsulation surrounding the stud further provides increased channel reliability. The improved uniformity of the photoresist aperture achieved for each step in the stud structure, and lower current spreading resistance because of the wider underlying stud base size, increases stud uniformity resulting in improved stud yields. This increased yield compared with conventional single step stud processes reduces cost, even with the additional photolithography and plating processes involved.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: April 23, 2002
    Assignee: Quantum Corporation
    Inventors: Vijay K. Basra, Lawrence G. Neumann