Abstract: Generally, the present invention provides a system and method for processing instructions of a computer program and for indicating instruction attribute and/or status information so that the efficiency of the processing system may be increased. In architecture, the system of the present invention utilizes a pipeline, a scoreboard, and hazard detection circuitry. The pipeline processes and executes instructions of a computer program. Many of the instructions include register identifiers that identify registers where data should be written when the instructions are executed. When the data produced by execution of one of the instructions has yet to be written to the register identified by the one instruction's register identifier and is unavailable for use in executing other instructions of the program, the one instruction's register identifier is transmitted to the scoreboard.

Abstract: A method and apparatus for predicting the outcome of a branch instruction based on the branch history of preceding branch instruction. As a sequence of instructions passes through an instruction execution pipeline, a base branch instruction is chosen, a history index is generated for the base branch instruction and subsequent branch instructions, and a transform is created for the branch instruction to be predicted. When the sequence of instructions subsequently passes through the pipeline again, the transform is used to operate on the history index of the base branch instruction to produce a history index for the branch to be predicted. The result is used as an index into a prediction array to access the prediction logic for the branch instruction being predicted. By using the predetermined transform, a branch status prediction can be made before the branch to be predicted reaches the normal prediction stage in the pipeline.

Abstract: A superscalar processing system that detects data hazards within instruction groups utilizes a memory, a plurality of pipelines, an instruction dispersal unit (IDU), and a control mechanism. The memory includes a plurality of entries that respectively correspond with a plurality of registers. The IDU receives an instruction group that includes a plurality of instructions and transmits the instructions of the instruction group to the plurality of pipelines. The control mechanism analyzes one of the instructions and identifies an entry in the memory that corresponds with a register associated with the one instruction. The control mechanism then analyzes the entry and transmits a warning signal in response to a determination that the entry indicates that another instruction within the instruction group is associated with the register.

Abstract: A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A row's select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each row's count vector is determined in two stages.

Abstract: A data processing apparatus for processing floating point instructions is responsive to a floating point instruction to apply a floating point operation to a number of operands to produce a final result, result data being generated during a predetermined pipelined stage with further processing then being performed on the result data in one or more subsequent pipelined stages to generate the final result. Exception determination logic determines whether an exception may occur during application of the floating point operation to the operands, and to prevent the execution unit applying the floating point operation to those operands if it is determined that an exception may occur. The exception determination logic is arranged to use at least some of the predetermined control data to compensate for differences between the forwarded result data and the final result relevant when determining whether an exception may occur when processing the second floating point instruction.

Abstract: A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.

Abstract: A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise “ORed” with an accrued exception field if a trap enable mask field is configured to mask the exception, with the “ORed” result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.

Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.

Abstract: A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline.

Abstract: A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

Abstract: A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle.

Abstract: A method of prefetching addresses includes the step of accessing a stored instruction using a current address. During the access using the current address, a target address is accessed in a branch target address cache. A stored instruction associated with the target address accessed from the branch target address cache is prefetched and the branch target address is indexed with selected bits from the address accessed from the branch target address cache.

Abstract: A processing system provides predicate data that indicates whether instructions processed by a processor pipeline should be executed by the pipeline. In architecture, the system of the present invention utilizes a register, a pipeline, and predicate circuitry. The pipeline includes a first stage and a second stage for processing instructions of a computer program. The predicate circuitry is configured to read a first predicate value from the register and to receive a second predicate value. The predicate circuitry may transmit the first predicate value read from the register to the first stage and then select between the first predicate value and the second predicate value. The predicate value selected by the predicate circuitry is transmitted to the second stage.

Abstract: Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units (7), to interpret that control information and take appropriate action.

Abstract: A bypass logic circuit (30) generates select signals (SelRs0, SelRt0, SelRs1 and SelRt1) by using prediction result flags (PrdNTkn1A and PrdNTkn1D) which are results of prediction about branch, instead of a branch condition not-taken signal (NTknA) actually output from a branch unit (52). Bypass multiplexers (44, 46, 54, 56) select operands to be output to ALU (42) or the branch unit (52) on the basis of these select signals (SelRs0, SelRt0, SelRs1 and SelRt1). Therefore, ample time is given for generating these select signals (SelRs0, SelRt0, SelRs1 and SelRt1).

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A user stack region (910) is used to pass variables to a subroutine and to hold values representative of a first portion of a program counter (1000). A system stack region (911) is used to hold values representative of a remaining portion of the program counter (1001) and to hold additional context information. The user stack region and the system stack region are managed independently so that software from a prior generation processor can be translated to run on processor (100).

Abstract: A processing device (10) provides general-purpose input/output pins (52) for use by software routines as needed. A data input register (54) has bits corresponding to each pin (52) for storing the value of the signal on the pin. A data output register (56) has bits corresponding to each pin for driving the signal on the pin (52) to a desired value. An output enable register (58) controls output buffers (62) coupled between the output register (56) and the pins (52). A plurality of mask registers (60) may be individually set to define a set a pins associated with the mask. Each of the data registers, the data input register (56), the data output register (58) and the output enable register (60) are accessed through a plurality of addresses, where the address specifies both the data register being accessed and an associated mask register (60). Logic (50) accesses the data registers in view of the state of the associated mask register (60).