Abstract: A process for fabricating stacked capacitor, DRAM devices, wherein the surface area of the capacitor is significantly increased as a result of sidewall processes, has been developed. The process is highlighted by deposition of polysilicon, to be used for the lower electrode of the stacked capacitor structure, on specific underlying insulator shapes. As a result of the severe underlying insulator topography, a significant portion of the polysilicon forms on the sides of the underlying insulator shapes, creating a significant increase in the lower electrode surface area, which relates to marked increases in capacitance and device signal.