Patents Examined by Toniae Thomas
  • Patent number: 9530618
    Abstract: A chuck, a system including a chuck and a method for making a semiconductor device are disclosed. In one embodiment the chuck includes a first conductive region configured to be capacitively coupled to a first RF power generator, a second conductive region configured to be capacitively coupled to a second RF power generator and an insulation region that electrically insulates the first conductive region from the second conductive region.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt
  • Patent number: 9525031
    Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Ken-Ichi Goto, Chia-Wen Liu, Yeh Hsu
  • Patent number: 9458012
    Abstract: A method includes applying a compressive force against MEMS structures at a front side of a MEMS wafer using a protective material covering at least a portion of the front side of the MEMS wafer. The method further includes concurrently dicing through the protective material and the MEMS wafer from the front side to produce a plurality of MEMS dies, each of which includes at least one of the MEMS structures. The protective material is secured over the front side of the MEMS wafer to apply pressure to the protective material, and thereby impart the compressive force against the MEMS structures to largely limit movement of the MEMS structures during dicing. A tack-free surface of the protective material enables its removal following dicing.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 4, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alan J. Magnus, Vijay Sarihan
  • Patent number: 9455178
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is deposited over the conductive feature and the substrate. A via-forming-trench (VFT) is formed in the first dielectric layer to expose the conductive feature and the substrate around the conductive feature. The VFT is filled in by a sacrificial layer. A via-opening is formed in the sacrificial layer to expose the conductive feature. A metal plug is formed in the via-opening to connect to the conductive feature. The sacrificial layer is removed to form a surrounding-vacancy around metal plug and the conductive feature. A second dielectric layer is deposited over the substrate to seal a portion of the surrounding-vacancy to form an enclosure-air-gap all around the metal plug and the conductive feature.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Lun Kao, Tien-Lu Lin, Yung-Chih Wang, Cheng-Chi Chuang
  • Patent number: 9431296
    Abstract: A contact structure with improved contact resistance and reliability is provided by forming an inner spacer between a contact liner and dielectric layers laterally surrounding the contact structure. The inner spacer severs as a barrier to prevent diffusion of metals from the contact liner into the dielectric layers.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9406909
    Abstract: An organic light emitting transistor increases the amount of charge induced into an organic layer, and a display device includes the organic light emitting transistor. The organic light emitting transistor includes a substrate, an organic semiconductor layer positioned on the substrate, a source electrode and a drain electrode spaced apart from each other while contacting the organic semiconductor layer, a gate electrode insulated from the organic semiconductor layer, the source electrode and the drain electrode and positioned to overlap the organic semiconductor layer, and an auxiliary electrode overlapping the source electrode or the drain electrode.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 2, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Ki Seo Kim
  • Patent number: 9396934
    Abstract: Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 19, 2016
    Assignee: ASM IP Holding B.V.
    Inventor: John Tolle
  • Patent number: 9385247
    Abstract: A method of forming an oxide layer on an exposed surface of a semiconductor device which contains a p-n junction is disclosed, the method comprising: immersing the exposed surface of the semiconductor device in an electrolyte; producing an electric field in the semiconductor device such that the p-n junction is forward-biased and the exposed surface is anodic; and electrochemically oxidizing the exposed surface to form an oxide layer.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: July 5, 2016
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Valantis Vais, Alison Joan Lennon, Stuart Ross Wenham, Jing Jia Ji, Alison Maree Wenham, Jingnan Tong, Xi Wang
  • Patent number: 9318582
    Abstract: After forming a gate spacer on each sidewall of a sacrificial gate structure, portions of each dielectric fin cap portion underneath the gate spacer is intentionally etched and undercut regions that are formed are filled and pinched off with a dielectric material of a conformal dielectric liner. Portions of the conformal dielectric liner in the undercut regions are not subject to the undercut during an epitaxial pre-clean process performed prior to forming an epitaxial source region and an epitaxial drain region on opposite sides of the sacrificial gate structure and remain in the undercut regions after forming the epitaxial source region and the epitaxial drain region.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Sreenivasan Raghavasimhan
  • Patent number: 9299730
    Abstract: A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode and having an opening, and the upper electrode is insulated from the lower electrode by a second insulation layer; an inter-layer insulation film covering the capacitor; a node contact hole in the inter-layer insulation film and the second insulation layer, and within the opening; and a connection node on the inter-layer insulation film and electrically coupling the lower electrode and at least one TFT to each other through the node contact hole.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 29, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Se Lee, Won-Kyu Kwak, Se-Ho Kim
  • Patent number: 9293332
    Abstract: A selective crystallization method includes placing a first substrate including first crystallization regions on a second substrate including second crystallization regions such that the first crystallization regions and the second crystallization regions are arranged alternately, and crystallizing the alternately-arranged first crystallization regions and the second crystallization regions with a laser beam. A laser crystallization apparatus can be used in the selective crystallization method.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 22, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Do-Young Kim, June-Woo Lee, Won-Kyu Lee
  • Patent number: 9287374
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region, a device isolation film, a first liner nitride film disposed over a lower portion of a sidewall of the active region, and a second liner nitride film disposed over an upper portion of the sidewall of the active region and having a higher density of nitrogen than a density of nitrogen in the first liner nitride film.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: March 15, 2016
    Assignee: SK HYNIX INC.
    Inventors: Yu Jun Lee, Kyoung Chul Jang
  • Patent number: 9282638
    Abstract: A method of forming a low-resistance, high-reliability through/embedded electrode is provided, where the electrode can be arranged in a higher density according to the miniaturization of the semiconductor manufacturing technology. This method includes the step of filling an opening 51 of a substrate 50 with a paste 56 of a first conductive material and drying the paste 56; the step of solid-phase sintering the paste 56 filled in the opening 51, generating a first porous conductor 57; the step of applying a paste of a second conductive material so as to cover the first conductor 57; and the step of melting the paste of the second conductive material by heat treatment, impregnating the second conductive material into the first conductor 57.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: March 8, 2016
    Assignee: ZYCUBE CO., LTD.
    Inventors: Manabu Bonkohara, Hirofumi Nakamura, Qiwei He
  • Patent number: 9281402
    Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • Patent number: 9269636
    Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: February 23, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam Nandakumar, Hiroaki Niimi
  • Patent number: 9257527
    Abstract: A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: February 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9252233
    Abstract: The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Rou-Han Kuo, Ting-Fu Lin, Sheng-Fu Yu, Tzung-Da Liu, Li-Yi Chen
  • Patent number: 9252021
    Abstract: Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hoi-Tou Ng, Kuei-Liang Lu, Ming-Feng Shieh, Ru-Gun Liu
  • Patent number: 9236267
    Abstract: A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho Wei De, Kuei-Liang Lu, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 9209291
    Abstract: A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: December 8, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin Ho Bin, Ki Hong Lee