Abstract: Memory circuits that read the bit state of memory cells are disclosed. In some embodiments, a memory circuit, includes a memory cell configured to store a bit. A reference line is configured to receive a reference signal and a data line is configured to receive a data signal. The data line is configured to be selectively coupled to the memory cell. A charge voltage select unit is configured to charge the reference line and the data line in response to a select signal being in a first select state and discharge the reference line and the data line in response to the select signal being in a second select state. A sense amplifier is configured to compare the data signal and the reference signal to sense a bit state of the bit stored by the memory cell.

Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for regulators providing shared current from multiple input supplies. A regulator can include a first portion configured to receive a first supply voltage and to output a first current drawn from the first supply voltage by a load, and a second portion configured to receive a second supply voltage. The regulator can include a current control circuit configured to, responsive to a load current corresponding the load meeting a particular criteria, initiate current sharing such that the load current is subsequently shared between the first supply voltage and the second supply voltage.

Abstract: An apparatus for generating a binary numerical sequence is provided. The apparatus is configured to apply a first write voltage or a second write voltage, different from the first write voltage, as a write voltage to each of two or more switchable elements, and/or to apply a first read voltage or a second read voltage, different from the first read voltage, as a read voltage to each of the two or more switchable elements. Each switchable element of the two or more switchable elements is configured to output, in dependence on the write voltage applied to the switchable element and/or in dependence on the read voltage applied to the switchable element, an output voltage with a first random or pseudo-random voltage value from a first voltage value range or with a second random or pseudo-random voltage value from a second voltage value range.

Abstract: Disclosed is a memory device which includes a plurality of memory banks and control logic. The control logic receives a plurality of column address bits and a plurality of read commands. The control logic includes a processing-in-memory (PIM) address generator. In a first operation mode, the control logic sends the plurality of column address bits to a memory bank. In a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.

Abstract: A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.

Abstract: An auxiliary power supply includes an auxiliary power storage configured to store power that is input to the auxiliary power supply and a control circuit, wherein the control circuit is configured to charge, for a reference time amount after the power is input to the auxiliary power supply, the auxiliary power storage by a first current source having a preset peak current level, determine, after the reference tune amount, that the auxiliary power supply is in a slow charging state when a voltage level that is charged to the auxiliary power storage by the first current source for the reference time amount is lower than a reference voltage level, and increase, in response to the slow charging state, the peak current level to charge the auxiliary power storage by a second current source having the increased peak current level that is greater than the preset peak current level.

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

Abstract: Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test using a data mask inversion (DMI) bit. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first DMI bit of the memory device that is associated with indicating a status of the memory built-in self-test and a second DMI bit of the memory device that is not associated with indicating the status of the memory built-in self-test. The memory device may set the first DMI bit to a first value based on the one or more bits indicating that the memory built-in self-test is enabled. The memory device may perform the memory built-in self-test based on setting the first DMI bit to the first value.

Abstract: A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer.

Abstract: Disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. The apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.

Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

Abstract: A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.

Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.

Abstract: Disclosed is a MIMO FIFO buffer circuit that reads out data flits at once as many as an internal pointer increment value. The MIMO FIFO buffer circuit includes a MIMO FIFO storage array including ‘Y’ storage blocks, and an internal pointer generator that generates an internal pointer based on an internal pointer increment value indicating the number of data flits to read out at once from among ‘K×X’ data flits stored in K storage blocks out of the ‘Y’ storage blocks. Each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’, and each of the ‘K’ storage blocks stores ‘X’ data flits.

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.