Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.

Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.

Abstract: Disclosed is a MIMO FIFO buffer circuit that reads out data flits at once as many as an internal pointer increment value. The MIMO FIFO buffer circuit includes a MIMO FIFO storage array including ‘Y’ storage blocks, and an internal pointer generator that generates an internal pointer based on an internal pointer increment value indicating the number of data flits to read out at once from among ‘K×X’ data flits stored in K storage blocks out of the ‘Y’ storage blocks. Each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’, and each of the ‘K’ storage blocks stores ‘X’ data flits.

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.