Patents Examined by Tran Q Tran
  • Patent number: 8030720
    Abstract: A back-illuminated type solid-state imaging device is provided in which an electric field to collect a signal charge (an electron, a hole and the like, for example) is reliably generated to reduce a crosstalk. The back-illuminated type solid-state imaging device includes a structure 34 having a semiconductor film 33 on a semiconductor substrate 31 through an insulation film 32, in which a photoelectric conversion element PD that constitutes a pixel is formed in the semiconductor substrate 31, at least part of transistors 15, 16, and 19 that constitute the pixel is formed in the semiconductor film 33, and a rear surface electrode 51 to which a voltage is applied is formed on the rear surface side of the semiconductor substrate 31.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 7465985
    Abstract: A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Yong Choi, Choong-Ho Lee, Dong-Gun Park
  • Patent number: 7453117
    Abstract: To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: November 18, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Naoaki Sudo, Kohji Kanamori
  • Patent number: 7432538
    Abstract: A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The channel is formed near the interface between the channel layer and the carrier supply layer or depleted, the carrier supply layer has a band gap energy greater than that of the channel layer, and x in the formula AlxGa1-xN decreases monotonically with an increase in the distance from the interface. The channel layer may be crystalline of gallium nitride. The channel layer may be undoped. X of the formula AlxGa1-xN of the carrier supply layer is greater than or equal to 0.15 and less than or equal to 0.40 at the interface.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: October 7, 2008
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Kosaki, Koji Hirata
  • Patent number: 7420246
    Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: September 2, 2008
    Assignee: DENSO CORPORATION
    Inventors: Shoji Ozoe, Tomofusa Shiga, Yoshifumi Okabe, Takaaki Aoki, Takeshi Fukazawa, Kimiharu Kayukawa
  • Patent number: 7400022
    Abstract: A photoreceiver cell with separation of color components of light incident to its surface, formed in a silicon substrate of the conductivity of the first type with an ohmic contact and comprising: the first, second and third regions, which have mutual positioning and configuration, which provide formation of the first and the second channels for diffusion of the secondary charge carriers generated in the substrate regions located under the first and the second potential barriers to the first and the third p-n junctions respectively; in this case, the length of the channels does not exceed the diffusion length of the secondary charge carriers. A technical result of the present invention is an increase in spatial resolution of the projected image and its dynamic range. Another technical result of the present invention is a decrease in the photo-cell area. A photoreceiver cell with color separation may find broad application in multielement photoreceivers for video cameras and digital cameras.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: July 15, 2008
    Assignee: Unique IC's
    Inventors: Yuriy Ivanovitch Tishin, Victor Alexandrovitch Gergel, Vladimir Alexandrovitch Zimoglyad, Igor Valerievitch Vanushin, Andrey Vladimirovitch Lependin
  • Patent number: 7385263
    Abstract: The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: June 10, 2008
    Assignee: Atmel Corporation
    Inventors: Maud Pierrel, Bilal Manai