Patents Examined by Tran Tran
  • Patent number: 10199491
    Abstract: A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: February 5, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Rainald Sander, Markus Winkler, Michael Asam, Matthias Stecher
  • Patent number: 10199462
    Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: February 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Xiangdong Chen
  • Patent number: 10193039
    Abstract: A method of manufacturing a light emitting element mounting base member includes: arranging a plurality of core members each including an electrical conductor core and a light-reflecting insulating member provided on a surface of the electrical conductor core; cutting the arranged core members to form a base member preparatory body including at least one cut surface on which at least one of the electrical conductor cores and the insulating members are exposed; and insert molding by placing the base member preparatory body in a set of mold, and injecting a light blocking resin composition into the set of mold such that at least one of the electrical conductor cores or at least one metal film formed on at least one of the electrical conductor cores are exposed on at least one outer surface of the light emitting element mounting base member.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: January 29, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 10163841
    Abstract: A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Jui-Pin Hung, Der-Chyang Yeh
  • Patent number: 10153263
    Abstract: A structure of a patterned material layer including separate patterns arranged in rows and columns is described. The separate patterns in at least one row including the outmost row each have a larger dimension in the column direction than the separate patterns in the other rows. The separate patterns in at least one column including the outmost column each have a larger dimension in the row direction than the separate patterns in the other columns.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 11, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chin-Cheng Yang, Chia-Hua Lin, Chih-Hao Huang
  • Patent number: 10147871
    Abstract: A magnetic memory device may include a magnetic tunnel junction pattern that comprises a tunnel barrier pattern, a first magnetic pattern and a second magnetic pattern, a tunnel barrier pattern between the first and second magnetic patterns, a non-magnetic pattern on the second magnetic pattern, and a magnetic material between at least a distal portion of the non-magnetic pattern and the second magnetic pattern. The magnetic material may include a set of fine magnetic patterns between the second magnetic pattern and the non-magnetic pattern, the set of fine magnetic patterns including a pattern of fine magnetic patterns spaced apart from each other in a direction parallel to an interface between the second magnetic pattern and the non-magnetic pattern. The magnetic material may include magnetic atoms, and the non-magnetic material may include a proximate portion that is proximate to the second magnetic pattern, the proximate portion doped with the magnetic atoms.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sungmin Ahn
  • Patent number: 10141280
    Abstract: Structures and formation methods of a package structure are provided. The package structure includes a semiconductor die and a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween. The first bonding structure and the second bonding structure are next to each other and the second bonding structure is wider than the first bonding structure. The first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump thereon, and the second bonding structure has a second UBM structure and a second solder bump thereon. The second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hsien-Wei Chen
  • Patent number: 10133137
    Abstract: A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD
    Inventors: Kyung-Ho Park, Bo-Yeong Kim, Jae-Won Kim, Byoung-Sun Na, Hyung-Jun Park, Dong-Hyun Yoo, Kye-Uk Lee
  • Patent number: 10109741
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10096625
    Abstract: A thin film transistor (TFT) includes a scan line on a substrate, the scan line including a straight portion extending along a first direction, an active layer including an oxide semiconductor and overlapping the straight portion of the scan line, the active layer having a first region, a second region, and a third region that are linearly and sequentially aligned along the first direction, a first insulating layer between the active layer and the scan line, a first electrode connected to the first region of the active layer, and a second electrode connected to the third region of the active layer.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: October 9, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Mi Hwang, Young-Bae Jung
  • Patent number: 10096651
    Abstract: A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: October 9, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jianhua Yang, Ning Ge, Katy Samuels, Minxian Max Zhang
  • Patent number: 10090251
    Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Peter Ossimitz, Gottfried Beer, Juergen Hoegerl, Andreas Munding
  • Patent number: 10083996
    Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 10074561
    Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed using a device layer of the silicon-on-insulator substrate. A trap-rich layer is between a substrate and a buried insulator layer of the silicon on-insulator substrate. An electrically-conducting connection is located in a trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate. The electrically-conducting connection at least partially comprised of trap-rich material.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 10074307
    Abstract: Disclosed herein is a display device in which light emitting elements of a plurality of colors including a light emitting element emitting blue light are formed in each pixel on a substrate on which a transistor is formed for each sub-pixel, and a plurality of pixels formed with sub-pixels of the plurality of colors as a unit are arranged in a form of a matrix, wherein relative positional relation between transistors of sub-pixels of respective light emission colors including blue light and a light emitting section of a light emitting element emitting the blue light is laid out such that distances between the transistors of the sub-pixels of the respective light emission colors including the blue light and the light emitting section of the light emitting element emitting the blue light are equal to each other for the respective colors.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 11, 2018
    Assignee: Sony Corporation
    Inventors: Tetsuo Minami, Katsuhide Uchino
  • Patent number: 10062791
    Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 28, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Po-Li Shih, Chih-Lung Lee, Hsin-Hua Lin
  • Patent number: 10043833
    Abstract: A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Takuro Ohmaru
  • Patent number: 10020418
    Abstract: Techniques for integrating spalling into layer transfer processes involving optical device semiconductor materials are provided. In one aspect, a layer transfer method for an optical device semiconductor material includes forming the optical device semiconductor material on a first substrate; depositing a metal stressor layer on top of the optical device semiconductor material; attaching a first handle layer to the metal stressor layer; removing the optical device semiconductor material from the first substrate by pulling the first handle layer away from the first substrate; attaching a second handle layer to the optical device semiconductor material; removing the first handle layer from the stack; and forming a second substrate on the stressor layer. Vertical LED devices and techniques for formation thereof are also provided.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 10014465
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer has an interface with a tunnel barrier and a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or CoXFeYNiZLW wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing at about 400° C. thereby promoting BCC structure growth in the oxide layer. As a result, free layer PMA is enhanced and maintained to yield improved thermal stability.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Mari Iwata
  • Patent number: 10002791
    Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee