Abstract: In the computer apparatus which has a processing unit, a power consumption measuring unit, and a power counter, the power consumption of running programs on the processing unit is measured at arbitrary constant period, wherein the measuring value is integrated to the power counter. When the power counter overflows, the processing unit is interrupted for sampling information required for analysis. Then the processing unit which received the interruption executes a sampling of the power consumption base. So, power consumption based sampling and profiling becomes to be enabled.

Abstract: An I2C multi-slot circuit system includes a plurality of I2C slots for receiving a plurality of slave processors, a CPU, a logic control unit, and a I2C switch unit. The CPU determines an address of one of the I2C slots which to-be-transmitted data will be transmitted to, and generates a first logic control signal according to the determined address. The logic control unit enables the one of the I2C slots which the to-be-transmitted data will be transmitted to according to the first logic control signal. The I2C switch unit receives and transmits I2C signal converted from the to-be-transmitted data by the CPU to the I2C slot. A related method is also provided.

Abstract: A motherboard includes a processor, a platform controller hub (PCH), a switch, a power connector, a switch unit, and an expansion slot. The PCH is connected to the expansion slot to output a bus signal to a serial advanced technology attachment dual in-line memory module (SATA DIMM), which is connected to the expansion slot, in response to the movement of a switch. The processor connected to the processor socket outputs a bus signal to an expansion card, which is connected to the expansion slot, in response to another movement of the switch.

Abstract: A storage system includes: a basic apparatus for transmitting an access request through a data input line for transmitting data; and an extension apparatus for receiving an access request from the basic apparatus through the data input line, the extension apparatus including a storage for storing data and a controller for controlling the access request from the basic apparatus, wherein the basic apparatus superimposes a voltage to the data input line in accordance with the access request, and wherein the extension apparatus includes an upper input voltage detector for detecting the voltage superimposed on the upper data input line and includes a power controller for controlling the power supply to the controller on the basis of the detected voltage.

Abstract: A method is provided for operating a data processing system having a memory. The memory is coupled between a first power supply voltage terminal for receiving a first variable potential and a second power supply voltage terminal for receiving a second variable potential. An initial difference between the first variable potential and the second variable potential is not less than a first voltage. The method comprises: receiving a command to transition the data processing system from a first power supply voltage to a second power supply voltage; changing the second variable potential so that a difference between the second variable potential and the first variable potential is greater than the first voltage; and after changing the second variable potential, changing the first variable potential, wherein a difference between the first variable potential and the second variable potential is not less than the first voltage.

Abstract: A method is provided for interfacing a plurality of processing components with a shared resource component. A token signal path is provided to allow propagation of a token through the processing components, wherein possession of the token by a given processing component enables the latter to conduct a transaction with the shared resource component. Token processing logic is also provided for propagating the token from one processing component to another along the token signal path, the propagating being done at a propagation rate that is related to a transaction rate associated with the shared resource component. The token processing logic also generates a trigger signal at least in part based on the token and propagates to trigger signal to the shared resource component to convey initiation of a transaction with the shared resource component.

Abstract: A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path.

Abstract: A USB hub utilizes an external power supply connection and rechargeable battery to provide a fully functional USB hub that provides portable backup power for USB devices. The hub includes a housing with a host connector that is adapted to be coupled to a host. Device connectors are also positioned on the housing that are adapted to be coupled to electronic devices. A hub circuit enables USB communications between the devices and host connected to the hub. The rechargeable battery is selectively charged from the host or external power supply connection. A microcontroller controls the hub circuitry such that power is provided to the hub circuit and the device connectors from an external power source or host if available or the rechargeable battery if they are not.

Abstract: A computer system with power source control and a power source control method are presented. The computer system at least includes a first storage unit and a second storage unit, and the first storage unit stores a system program required by the computer system in basic operation. A switch is disposed on a power supply path between a power supply module and the second storage unit, such that the power supply module provides an electric power for the second storage unit to operate through the switch. When the second storage unit is in an idle state, the switch is used to cut off the power supply to the second storage unit, so as to effectively reduce the power consumption of the computer system.

Abstract: One embodiment is a clocking system for a computing environment. The system comprises a first set of processes executing in a first computing environment; a first local clock mechanism associated with the first set of processes; and a first communications channel for connecting the first local clock mechanism with the first set of processes. The first local clock mechanism stores clock rates of the first set of processes, wherein each clock rate is specified by function and source and destination combination, the first local clock mechanism further coordinating the clock speeds of the first set of processes as necessary.

Abstract: Power is routed from one or more power supplies. As consistent with one or more example embodiments, a data storage device senses and/or is informed of the availability and voltage level of one or more power supplies. Based upon the availability and voltage level of power supplies, circuits in the memory device are powered using one or more of the sensed power supplies. In some applications, the power is drawn in a manner that emulates the behavior of one or more circuits that are respectively powered.

Abstract: A system and method for configuring expansion bus links to generate a double-bandwidth link slot are disclosed. An information handling system includes a central processing unit (CPU) and memory operable to store program instructions executable by the CPU. A chip set operably couples the CPU and the memory to a first slot and a second slot. The chipset includes a root port that generates a first link coupled to the first slot and a second link coupled to the second slot. An adapter card is inserted into either of the first or second slots such that the adapter card routes either the first or second link to the slot not populated by the adapter card.

Abstract: Techniques for communications based power management are described. An apparatus may comprise a managed power system having a communications sub-system and a computing sub-system, the communications sub-system to include a network state module operative to determine communications power state information, and send a power management message with the communications power state information. The apparatus may further comprise a power management module to receive the power management message, retrieve the communications power state information from the power management message, and manage power states for the computing sub-system based on the communications power state information. Other embodiments are described and claimed.

Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data-storage device is implemented having a memory control circuit controlling nonvolatile and volatile memory. An operating power circuit carries primary-operating power from the host-system to the memories and control circuitry. A backup power circuit includes energy-storage circuitry with one or more energy storage devices. An isolation-regulation circuit provides voltage regulation of power from the host-system and also isolates the host-system provided power from the energy storage devices. A regulation power circuit carries the regulated power from the isolation-regulation circuit to the energy storage devices.

Abstract: An arbitration diagnostic circuit and method provide diagnostic information in arbitration-based systems and/or provide detection of and response to excessive arbitration delays. For example, in one embodiment, an arbitration diagnostic circuit maintains a chronological memory trace of arbitration events, including resource request events and corresponding resource grant events for two or more entities having arbitrated access to a shared resource. The trace, which may be regarded as a running, ordered list, may comprise time-stamped event identifiers, which aid the analysis of arbitration related errors or failures. Indeed, in one or more embodiments, an arbitration diagnostic circuit is configured to track elapsed times for resource requests, and to detect resource grant delay violations.

Abstract: In one embodiment, a solid-state drive contains a plurality of data memory devices requiring elevated voltages for erasure and programming operations. A common voltage regulator, external to the data memory devices, provides the elevated voltage, thereby reducing the overall power consumption of the data storage device.

Abstract: A power supply unit includes a communication unit and a control unit. The communication unit is capable of performing communication with a first processing unit group constituted of a plurality of processing units connected thereto. The control unit controls powers to the plurality of processing units through the communication so that the powers are turned on in an order corresponding to an order of connection and assigns, to the plurality of processing units, respectively, IDs of numbers corresponding to the order of turning-on of the powers each time the power is turned on.

Abstract: The invention is a portable electronic device comprising a non volatile memory and a memory controller. The portable electronic device comprises a connector having eight pads able to communicate using a protocol of Secure Digital® type. The connector comprises at least one additional pad intended to be linked to an antenna. The additional pad is able to communicate using a protocol of SWP type.

Abstract: A bus-protocol converting device includes: a command detecting unit that detects a command sent from an external-memory control device, connected to a primary bus, to a primary bus interface controller; a command converting unit that converts the detected command into a command to be sent from a secondary bus interface controller to an external memory device through a secondary bus; a status detecting unit that detects a status sent from the external memory device; a status converting unit that converts the detected status into a status to be sent from the primary-bus interface controller to the external-memory control device through the primary bus; and a data transfer controller that is provided between the primary bus interface controller and the secondary bus interface controller to perform data transfer between the external-memory control device and the external memory device through a DMA bus.

Abstract: The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to the interrupt processing. An interrupt generation unit 140 generates an interrupt signal. An interrupt status holding unit 142 stores an interrupt status showing a cause of generation of the interrupt signal. An interrupt status supply unit 141 supplies an interrupt status stored by an interrupt status holding unit to a RAM and causes the RAM to store it. A CPU executes a predetermined processing in response to the interrupt status stored to the RAM. The present invention can be applied to, for example, a network card.