Abstract: In a method of designing/manufacturing a plurality of semiconductor integrated circuit devices having built-in ROMs each storing different data on a single wafer, a ROM pattern is formed in combination with a pattern that is common to a plurality of semiconductor integrated circuit devices other than the ROM pattern.

Abstract: During the preconditioning of word lines (19) of a memory array (10), Each nondefective word line (19) is fired, one at a time, to raise the turn-on voltage of the word line. After each nondefective word line (19) has been fired, physically adjacent word line groupings (35) are fired simultaneously without regard to the presence of defective word lines (19).

Abstract: Integrated circuit memory devices and operating methods map a plurality of memory cell blocks excluding defective memory cell blocks into a continuous address sequence of variable length. The memory cell blocks excluding the defective memory cell blocks, are preferably mapped to defective normal memory cell blocks, beginning at a highest memory cell block address and sequentially proceeding to lower cell block addresses, so as to generate continuous addresses for the memory cell blocks. Continuous address spaces may be provided by providing a plurality of flag blocks, a respective one of which corresponds to a respective one of the normal memory cell blocks. Each flag block contains a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, or a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block.

Abstract: A static random-access memory (SRAM) cell with one or more storage elements connected to a sensing component by a single transmission line. Each storage element is connected to the transmission line through a switch so that one storage element at a time can be actively connected to the transmission line. The sensing component produces an output indicating the value stored in the active storage element then switched onto the transmission line.

Abstract: An input buffer circuit includes a first amplifier causing a first change in an output signal by detecting a rising edge of an input signal, a second amplifier causing a second change in the output signal by detecting a falling edge of the input signal, and a feedback path feeding back the output signal as a feedback signal to the first amplifier and the second amplifier. The feedback signal controls the second amplifier such that a timing of the first change only depends on the first amplifier, and controls the first amplifier such that a timing of the second change only depends on the second amplifier.