Abstract: A switched capacitor circuit (10) is responsive to a two phase repetitive clock signal comprised of alternating periods (.phi.1) and (.phi.2). The circuit includes a first input branch including a first amplifier (A) for charging a first capacitance (C1) from a first input signal during period (.phi.2). The circuit further includes a second input branch that includes a second amplifier (B) for charging a second capacitance (CA) from a second input signal during a period (.phi.1A), and for charging a third capacitance (CB) from the second input signal during a period (.phi.1B); wherein (.phi.1A) and (.phi.1B) alternate in occurrence with one another during successive (.phi.1) periods. The circuit further includes switches for coupling the first capacitance and the second capacitance to an input of an output amplifier (C) during (.phi.1B), and for coupling the first capacitance and the third capacitance to the input of the output amplifier during (.phi.1A).

Abstract: A single event upset immune latch circuit comprises a first latch having first and second complementary channel inverters respective input nodes and output nodes of which are cross-coupled to one another. First second pairs of (complementary channel) decoupling transistors respectively couple the output nodes of said first and second complementary channel inverters in circuit with first and second voltage supply terminals. (Cross-)coupled with the first latch is a second latch having third and fourth complementary channel inverters, respective input nodes and output nodes of which are cross-coupled to one another. Third and fourth pairs of (complementary channel) decoupling transistors respectively couple the third and fourth complementary channel inverters in circuit with the first and second voltage supply terminals.