Abstract: In a Viterbi decoder including an add-compare-select (ACS) processor, speed is enhanced without loss of performance by maintaining a dynamic cumulative metric range for computed state metrics. Current state metrics are added to new branch metrics to obtain two computed metrics, and the smaller of the two computed metrics is stored along with previously computed state metrics. The stored state metrics are compared with a selected scale factor, for example one-half maximum scale factor, and all current state metrics are rescaled when the minimum stored metric value exceeds the selected scale factor.

Abstract: A digitally modulated signal of the FSK type is subjected to limiting and linear FM demodulation to produce a baseband signal which often fails to show clearly the serial binary digital signal because of distortion and disturbances prior to its reception. The amplitude of the base-band signal is digitally sampled (quantized) at a uniform sampling rate which is an integral multiple of the symbol rate of the base-band signal. A sequence of successive amplitude samples spanning at least a symbol period addresses, at twice the symbol rate a look-up table containing a set of stored signal patterns and correspondence of patterns within a predetermined degree of similarity is elicited at twice the symbol rate along with information on the degree of similarity, and also a synchronizing pulse when the amplitude pattern shows that a binary signal transition is detected at a particular part of the pattern of the amplitude sample sequence.