Abstract: A semiconductor device includes a line; a source structure on the line; a stack structure on the source structure; a first slit structure penetrating the stack structure; a second slit structure penetrating the stack structure; and a contact plug adjacent to the first slit structure in a first direction. The first slit structure and the second slit structure may be spaced apart from each other by a first distance in a second direction that is perpendicular to the first direction. The contact plug penetrates the source structure, the contact plug being electrically connected to the lower line. The first slit structure and the contact plug may be spaced apart from each other by a second distance in the first direction, and the second distance may be longer than the first distance.

Abstract: A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

Abstract: A semiconductor memory device according to the present embodiment includes a semiconductor substrate, a structure including a plurality of insulating films and a plurality of conductive films alternately stacked on the semiconductor substrate, and a pillar penetrating the structure. The plurality of conductive films include a plurality of first conductive films and a second conductive film arranged closer to the semiconductor substrate than the plurality of first conductive films. The pillar has a first epitaxial growth layer doped with boron and carbon in a part in contact with the semiconductor substrate, and configured to functions as a part of a source side select gate transistor together with the second conductive film. The plurality of first conductive films configured to functions as a part of a plurality of non-volatile memory cells.

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

Abstract: A semiconductor device includes a substrate including a memory cell region and a peripheral circuit region, the peripheral circuit region including a first peripheral circuit region including a first transistor and a second peripheral circuit region including a second transistor; a storage node contact plug positioned in an upper portion of the substrate in the memory cell region; a landing pad over the storage node contact plug; a first metal wire coupled to the first transistor; and a second metal wire coupled to the second transistor, wherein a thickness of the landing pad and a thickness of the first metal wire are smaller than a thickness of the second metal wire.

Abstract: A semiconductor memory device according to an embodiment includes a substrate including block areas, members, conductive layers, and pillars. Each of the members is respectively disposed at a boundary portion between the block areas. At least one member of the members includes first portions and a second portion. The first portions are arranged in a first direction. The second portion is disposed between any two adjacent ones of the first portions. Either one of one of the first portions and the second portion of the member is referred to as a third portion. The other one of the one of the first portions and the second portion of the member is referred to as a fourth portion. The third portion has a width in a second direction greater than a width of the fourth portion in the second direction.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. A channel-material string is in individual channel openings in the vertically-alternating first tiers and second tiers. A conductor-material contact is in the individual channel openings directly against the channel material of individual of the channel-material strings. The conductor-material contacts are vertically recessed in the individual channel openings. A conductive via is formed in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening. Other aspects, including structure independent of method, are disclosed.

Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.

Abstract: A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrOx and the charge trap structure includes a blocking layer, a charge trap layer, and a tunneling layer.

Abstract: A stack package includes a core die disposed over a package substrate, and a controller die disposed between the core die and the package substrate to control the core die. The core die includes banks each including memory cell arrays, an interbank region in which row decoders and column decoders are arranged, and a pad region in which first connection pads electrically connected to the row decoders and column decoders through first wirings are disposed. The controller die includes a through via region in which controller die through vias penetrating the controller die to be connected to the first connection pads are disposed, and a circuit region in which controlling circuitry electrically connected to the controller die through vias through second wirings is disposed.

Abstract: A semiconductor storage device includes: a first conductive layer extending in a first direction; a second conductive layer that is disposed apart from the first conductive layer in a second direction intersecting the first direction, and extends in the first direction; a plurality of semiconductor layers provided between the first conductive layer and the second conductive layer and arranged in the first direction, each of which includes a first portion facing the first conductive layer, and a second portion facing the second conductive layer; a plurality of first memory cells provided between the first conductive layer and the semiconductor layers, respectively; and a plurality of second memory cells provided between the second conductive layer and the semiconductor layers, respectively. A gap is provided between the two semiconductor layers adjacent in the first direction.

Abstract: A first gate wiring layer is a 2-layered structure in which a polysilicon wiring layer and a metal wiring layer containing aluminum are sequentially stacked. The polysilicon wiring layer and the metal wiring layer surround a periphery of an active region. In a portion of a periphery of the first gate wiring layer, the polysilicon wiring layer and the metal wiring layer contact each other via a contact hole of an interlayer insulating film and in remaining portions thereof, are electrically insulated from each other by the interlayer insulating film. The first gate wiring layer, in portion separate from a gate pad, is configured having relatively more of the metal wiring layer with a resistance value lower than that of the polysilicon wiring layer. The resistance value of the first gate wiring layer is adjusted to be relatively high in a portion near the gate pad, as compared to the portion separate from the gate pad.

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.

Abstract: According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.

Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.

Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

Abstract: A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.

Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.