Abstract: A method, an apparatus and a computer program product are disclosed for providing a lockeddown client environment in a client-server architecture of a computer network. In the method, an asset database is checked via the computer network to validate settings for configuration of the personal computer. The personal computer is booted using a personalized network boot disk for a user. The asset database contains information about the configuration of one or more personal computers. If the settings are validated, a lockeddown environment is built for the personal computer. The operating system and hardware drivers installed on the personal computer are dependent upon the asset database. The operating system prevents unauthorised modification and bypassing of the operating system. Preconfigured application software is installed on the personal computer dependent upon the asset database. User data can only be stored remotely at a server via the computer network.
Abstract: A hybrid tree data structure is suitable for use in scenarios involving intermingled text and user interface elements. Trees of two different types can be combined via one or more proxy nodes. For example, one type can be efficient at processing user interface elements and another can be efficient at processing text. Operations suitable for user interface elements can be efficiently performed on portions of the hybrid tree having user interface elements, and operations suitable for sequential data can be efficiently performed on portions of the hybrid tree having sequential data. The structure is thus suited for representing documents or graphical user interfaces. A hypertext document can be represented via the hybrid tree to enable more efficient searching, navigation, rendering, or editing of the document. Hybrid tree services can be provided by an operating system service.
Type:
Grant
Filed:
June 28, 2002
Date of Patent:
March 6, 2007
Assignee:
Microsoft Corporation
Inventors:
Peter Francis Ostertag, Michael J. Hillberg, Jeffrey L. Bogdan, Robert A. Relyea
Abstract: An interface definition that specifies the functionality of humanly accessed functions within a software program is parsed into statements by a parser in conjunction with a dictionary. The parsed statements are converted to formatted statements by a plurality of formatters resulting in expression of the interface definition in a plurality of selected formats. The selected formats comprise source code formats and various documentation formats. Files generated from source code formatters, such as “C++” formatters, are included in the software build process and facilitate restricting software development to the specified functionality. Changes to the interface definition are propagated to the selected formats resulting in software functionality that is consistent with the various forms of documentation such as on-line help and printed documentation.
Type:
Grant
Filed:
April 17, 2002
Date of Patent:
March 6, 2007
Assignee:
International Bussiness Machines Corporation
Abstract: In a software debugging apparatus, dump information formed by a hardware simulator is acquired and analyzed. When displaying the result of the analysis, information when software has operated hardware and information when the hardware has changed the value of an I/O register are separately displayed.
Abstract: A method of transferring files between a computer on board a train and a remote station including determining if the remote station is within range of the train and establishing wireless communication between the onboard computer and the remote station. Next, the computer determines whether there are files to be transferred, and if so, transfers the file. If the remote station has updates to be transferred to the train, such updates are transferred to the onboard computer. Files and updates are also transferred between remote stations and between remote stations and a home base station. A method of adjusting a simulator includes inputting data from the train onto a simulator. The simulator is operated with the data and the simulator automatically adjusts the parameters of the simulator until the data of the simulator matches the data from the train. The data can then be process and analyzed.
Type:
Grant
Filed:
September 24, 1999
Date of Patent:
March 6, 2007
Assignee:
New York Air Brake Corporation
Inventors:
Michael J. Hawthorne, Stephen K. Nickles, John E. Haley, Dale L. Sherwood
Abstract: A method and system for optimizing computer source code is provided. Prior to compiling the source code, the code is analyzed to determine the occurrence of repeating patterns of code. The repeating patterns of code are replaced with a programming loop that executes a single instance of the pattern multiple times using appropriate array indices and loop increments. In this manner, source code size is reduced making transfer, storage and compiling more efficient.
Abstract: A method for modifying serial dependencies in a procedure includes a step of building a graph representation of the procedure. The graph representation has an origin as well as a unique position, relative to the origin, for each memory operation in the procedure. Each memory operation in the representation is designated with a location type. Each of these location types are based on one or more characteristics of the corresponding memory operation that are sufficient to notify the compiler that the memory operation accesses a distinct or disjoint memory location. Memory operations having the same location type as subsequent memory operations are identified. When the graph representation does not include additional memory operations of the same location type between pairs of such memory operations, the subsequent memory operation is moved to a position in the intermediate representation that is closer to the origin.
Type:
Grant
Filed:
January 9, 2001
Date of Patent:
February 27, 2007
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: Embodiments of the present invention effectuate a method and system for debugging a device such as a microcontroller in a distributed architectural scheme, where the device may operate at speeds much faster than the debugger program is run, with limited debugging resources physically incorporated into the device itself, and with relatively limited computational capacity, vis-à-vis the platform deploying the debugging software. The embodiments place relatively modest, uncomplicated demands on the debugger software, and the ICE may also be relatively simple. Further, debugging methods and systems according to these embodiments are flexible and adaptable to a variety of different devices that must undergo debugging, yet remain effective, simple, and inexpensive.
Abstract: Colors to be used in register allocation are grouped into a number of sequences. Each sequence is associated with an attribute (e.g. size and/or type) of variables whose nodes in an interference graph can be colored by colors in the sequence. In certain embodiments, in addition to the above-described grouping, colors within a group are ordered in a sequence. The specific order that is used may depend on, for example, an attribute (such as size) and a predetermined preference. One example of such a predetermined preference is that a color that represents a register of the size that is associated with the sequence is located at the front of the sequence. Another color located later in the sequence represents a register of a different size than the size associated with the sequence.
Abstract: A method and apparatus for achieving a non-disruptive code load that includes staging the new version of executable code, stacking the hardware events during code copy and code switch over, copying the code into the runtime area, restarting the system upon completion of copying the new code without reinitializing the hardware and processing the stacked hardware events with the same system state (hardware and firmware) information.
Abstract: One embodiment of the present invention provides a system for type tagging values in a compiled activation frame in a lazy manner to facilitate garbage collection. This system operates in a mixed-mode environment that supports both interpretation of byte codes and execution of compiled native code. Upon receiving an invocation of a method, the system creates an activation frame for the method on the execution stack. If the method is executing in interpreted mode, the interpreter maintains a tag for each value in the activation frame during execution. The tag indicates whether the value is a reference type or a primitive type. However, if the method is executing in compiled mode, the system allocates space for tags for each value in the activation frame, but does not fill in the tags during execution. This allows the tags to be filled in at a future time when needed.
Abstract: Improved techniques for representation of Java data types in virtual machines are disclosed. The techniques can be implemented to represent signatures of Java methods as arrays of references. Each of the references in an array can represent a parameter for a Java method. Accordingly, a signature can be represented as an array of references, wherein each reference in the array can reference a Java type indicator or an internal class representation. The Java type indicator represents a Java primitive type (e.g., byte, integer, double, etc.) The internal class representation is typically the representation of a Java class as represented in a virtual machine. As will be appreciated, an array organization allows for more efficient access to information. Thus, unlike conventional techniques, there is no need to start at the beginning of the signature and sequentially read it to find a particular parameter's data type.
Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
Abstract: A method and system for organizing a package involving identifying an asset within an application, wherein the asset is determined by an asset boundary and the asset contains a logic/data part and an extended environment part; identifying the package within the application, wherein the package is a logical division of the application and wherein the package includes a plurality of assets; determining a package boundary identifying the scope of the package, wherein the package boundary may be determined by the asset boundary of at least one asset in the package; and organizing the package according to the package boundary, wherein the package including at least two assets.
Type:
Grant
Filed:
September 4, 2001
Date of Patent:
February 20, 2007
Assignee:
OP40, Inc.
Inventors:
Charles P. Pace, Paolo R. Pizzorni, Shuang Chen
Abstract: A method for compiling a mapping between a source schema and a target schema is provided. The method comprises multiple passes, including determining source node dependencies, matching hierarchy, and generating code. The method may further comprise initializing node dependency memory prior to determining source node dependencies, and freeing node dependency memory after code generation. The compiler algorithm provides for compiling user-defined functions in the mapping into the compiled representation. Another aspect of the invention provides for generating an XSL code representation of the mapping. An XSL style sheet representation may thus be generated from a visual mapping in accordance with the invention.
Abstract: An analyzer that analyzes instructions and data to determine where the instructions and data might result in incorrect results when run on a multiprocessor system. The instructions and data are divided into plural domains based on the symbols used to refer to those instructions and data, and the multiprocessor system is configured to use at most one processor at a time to execute instructions and to access data from any one domain. The analyzer preferably includes a reference analyzer and a table generator. The reference analyzer determines which of the instructions and data involve references outside of their domains, and determines which of the references outside of their domains are multiprocessor unsafe references. The report generator generates a report of the multiprocessor unsafe references. Also, a checker that dynamically determines where instructions and data result in domain violations when run on a multiprocessor system.
Type:
Grant
Filed:
April 5, 2001
Date of Patent:
February 13, 2007
Assignee:
Network Appliance, Inc.
Inventors:
Christopher Peak, Sathya Bettadapura, Jeffrey Kimmel
Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
Abstract: Provided are a computer implemented method, system, and program for translating a class schema in a source language to a target language. Class element definitions in a source file in the source language are received. The definitions of the class elements define instances of metadata types providing metadata for the class elements. Statements in the target language are generated to implement class elements defined in the source file. Statements are generated in the target language to define metadata elements for metadata types. For each metadata data type instance defined with one class element in the source file, at least one statement is generated in the target language to associate the metadata element generated for the metadata type with the implementation of the class element corresponding to the class element defined with the metadata type instance in the source file.
Abstract: A method for replacing a current operating software with a new operating software in a working network environment during network operations while also preserving a backup for the replaced operating software. The method including active or non-active memories based on the operating software stored therein. The active and non-active memories being interchangeable to accommodate the new operating software without stopping operation of the network or active memory.
Type:
Grant
Filed:
March 25, 2002
Date of Patent:
February 6, 2007
Assignee:
CIENA Corporation
Inventors:
Ruiping Wang, Peter Steele, Sundeep Mallya, Steve Langlois
Abstract: A method for distributing application, system and network specification information to functional elements controlling a plurality of hosts in a distributed environment, including steps for preparing specification files in a language providing a syntax adapted to describe application, system and network specification information, compiling the specification files to thereby generate specification objects, and providing an application programming interface (API) permitting the functional elements to access the specification information using API calls.
Type:
Grant
Filed:
May 24, 2001
Date of Patent:
January 30, 2007
Assignee:
The United States of America as represented by the Secretary of the Navy
Inventors:
Paul V. Werme, Larry A. Fontenot, Lonnie R. Welch