Abstract: An improved method of forming a semiconductor device structure is disclosed, comprising insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.
Abstract: An interconnect level includes upper and lower partial levels having respective conductive lines offset heightwise from each other. The interconnect level further includes respective dielectric portions separating adjacent conductive lines and extends above and below the conductive lines. At least one descending via connects a conductive line of the upper partial level with a lower element located below the dielectric portions of the interconnect level. The at least one descending via extends through the dielectric portions separating adjacent conductive lines of the lower partial level. At least one ascending via connects a conductive line of the lower partial level with an upper element located above the dielectric portions of the interconnect level. At least one ascending via extends through the dielectric portions separating adjacent conductive lines of the upper partial level.
Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.
Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to coupled the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.
Abstract: A metallizing system for silicon surfaces consists solely of two layers of nickel and silver, respectively. Approximately 2 microns of the underlying silicon surface is removed prior to metallization to ensure removal of an oxygen-saturated layer of silicon before the nickel layer is deposited. The assembly is heated sufficiently that the nickel layer forms a nickel-silicide layer at the silicon surface. The metallizing adheres to the bare treated silicon but does not adhere to adjacent oxide coatings and easily lifts off of oxide-coated surfaces. The metallizing is solderable, makes ohmic contact to the silicon, regardless of its conductivity type and survives subsequent alloy processing temperatures.
Abstract: Manufacturing of a graft-base transistor is characterized by: first, forming a layer (8) of oxide of silicon with opening on an n-semiconductor layer (2), at a part to become a base region (3, 4, 3) (FIG. 2a)); then, forming a polycrystalline silicon layer (9) and an overriding silicon nitride layer (10) with an opening (11) thereon (FIG. 2(b)); selectively diffusing P or As to form an n-emitter region (5) (FIG. 2(c)); forming a second silicon oxide layers (12, 13) only on the emitter region (5) and on peripheral regions thereabout, and removing the polycrystalline layer (9) and the silicon nitride layer (10), (FIG. 2(d)) (FIG. 2(e)); and implanting B.sup.+ ions, thereby to form deeper and higher concentration base contact regions (3, 3) and shallower and lower concentration active base region (4).
Abstract: The inventive method of manufacturing a semiconductor device is carried out by slicing a silicon single crystal grown by a Czochralski method, thereby to provide a wafer (1), annealing the wafer (1) at a temperature range of 600.degree. C. to 800.degree. C. in an atmosphere including an inert gas and a small amount of oxygen for approximately 2 to 6 hours, thereby to precipitate oxygen (2) in the whole wafer (1), and then annealing the wafer (1) in the temperature range of 1000.degree. C. to 1100.degree. C. in a water vapor atmosphere including chlorine, thereby to form an oxide film (3) on the surface of the wafer (1), whereby a denuded zone (4) is formed beneath the oxide film (3) while crystal defects (5a-5d, 6) serving as a getter of impurities such as metals are formed beneath the denuded zone.
Abstract: A method for manufacturing a semiconductor device, which comprises: a first process for producing a semiconductor layer of polycrystalline silicon or amorphous silicon on the surface of a substrate of insulator or a substrate made up by forming an insulating layer on a basic semiconductor; a second process for producing an island of semiconductor layer surrounded by dielectric materials from the semiconductor layer; a third process for producing a film of Si.sub.3 N.sub.4 on the island of semiconductor layer, or on a film of SiO.sub.2 formed on the island; a fourth process for removing the film of Si.sub.3 N.sub.4 at a predetermined region on the island; and a fifth process for irradiating with scanning an energy beam to the island of semiconductor layer so as to melt and recrystallize the island, thereby monocrystallizing or increasing the size of crystal grains at at least a partial region thereof.
Abstract: It is known to utilize dielectric-filled trenches in a CMOS integrated-circuit device to achieve electrical isolation between adjacent n-channel and p-channel regions. In that way, latchup-free operation of the device is ensured. But inversion effects along the walls of the trenches can cause high leakage currents, undesirably high parasitic capacitances and even shorting together of source/drain regions. In accordance with the invention, a nonlithographic technique including selective anodic oxidation is employed to selectively mask the sidewalls of the trenches. Each sidewall can then be independently doped thereby effectively eliminating the possibility of inversion occurring therealong.
Abstract: A process is disclosed for controllably providing dielectrically isolated semiconductor regions having a uniform and well defined thickness. Grooves are formed in a first surface of a semiconductor substrate and then a dielectric layer is formed covering that surface and the grooves extending into the surface. A layer of backing material such as polycrystalline silicon is formed overlying the dielectric layer. A semiconductor substrate is then thinned to form a new surface with portions of the dielectric layer and backing material exposed at that surface. A semiconductor layer is epitaxially grown overlying the new surface with the semiconductor layer having a monocrystalline structure where it is grown on exposed regions of the original substrate and having a polycrystalline structure otherwise. An oxidation masking layer is formed overlying those portions of the semiconductor layer which have a monocrystalline structure.
Abstract: A construction process employs an insulating abutment which serves as a guide in the formation of a shortlength electrode in the fabrication of a semiconductor device. The process is particularly useful in construction of extremely short channel asymmetric lightly doped drain (LDD) silicon FET's in which case a bird beak is formed on the surface of a silicon wafer. The bird beak is composed of silicon dioxide produced by oxidation of the silicon substrate with the aid of an oxidation resistant covering of silicon nitride, the edge of which defines the location of the abutment. Reactive ion etching is employed to remove excess silicon dioxide leaving a vertical wall at one side of the abutment. Thereafter, the silicon nitride layer is stripped off leaving a slating roof to the abutment. A dope polysilicon layer is deposited conformally on the surface of the substrate and on the abutment to a depth equal to the desired length of the electrode.
Abstract: A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.
June 28, 1984
Date of Patent:
March 17, 1987
International Business Machines Corporation
John R. Abernathey, Wayne I. Kinney, Jerome B. Lasky, Scott R. Stiffler
Abstract: A process for using selectively deposited tungsten in the making of ohmic contacts and contact/interconnect metallization patterns. In one form the process is employed to interconnect fully formed field effect devices using contacts through the dielectric layer. A thin layer of intrinsic polysilicon or amorphous silicon is conformally deposited, patterned and covered by selectively deposited tungsten, An anneal operation then forms self-aligned contacts or shunts, between the tungsten layer and the source/drain type diffusions exposed during the contact cut, by updiffusion through the thin intrinsic silicon, or by conversion of the thin intrinsic silicon to tungsten.
June 12, 1985
Date of Patent:
March 10, 1987
Werner A. Metz, Jr., Nicholas J. Szluk, Gayle W. Miller, Michael J. Drury, Paul A. Sullivan
Abstract: A mounting frame assembly (10) supports a semiconductor wafer (22) on an adhesively coated surface (18) of a polymer film (12). An inner mounting ring (16) and an outer mounting ring (17) feature complementary steps (47) and (52), respectively, which positively lock the outer ring (17) from moving with respect to the inner ring (16) during a wafer sawing operation in a direction of the plane wherein the wafer (22) is supported by the film (12).
Abstract: There is disclosed a method of manufacturing a semiconductor device comprising the steps of forming a polysilicon film on a semiconductor substrate through an oxidation film, forming a mask of a predetermined pattern on the polysilicon film, forming a molybdenum film on the polysilicon film, and silicifying those regions of said molybdenum film not covered by the mask so that a structure of the uncovered molybdenum film regions and those regions of the polysilicon film located under the uncovered molybdenum regions have low resistance, while a region of the molybdenum film covered by the mask has high resistance.
Abstract: Contacting an underlying region (e.g., doped silicon) through an access hole in an overlying dielectric layer (e.g., p-glass) formerly required flowing the dielectric to smooth the edges of the hole, so that aluminum would deposit smoothly into the hole. The present technique smoothes the side of the hole by forming a smoothing region on the sidewall. Improved aluminum coverage results, as well as allowing a smaller contact head, if desired. Improved contact resistance can be optionally provided by depositing a more conductive layer on the underlying layer prior to forming the sidewall.
Abstract: A novel lead frame structure is provided which contains an integral arrangement of leads for connection to a semiconductor device and a molded housing is then molded around the semiconductor device and the lead frame. The lead elements of the frame are then separated to define a plurality of individual semiconductor devices. The lead frame has an enlarged finger section which receives a semiconductor die. The enlarged lead frame finger has an opening just behind the region which receives the die. This opening as well as all identical openings along the length of the lead strip are then aligned with respective molding gates in one half of a pair of cooperating molding dies so that plastic injected through the gate flows through the opening and upwardly into the mold with the plastic filling the mold cavity from top to bottom while ejecting air from the mold as the mold fills through the clearance opening between the ejector pin and its receiving opening.
Abstract: An IR LED array and method of fabrication having a GaAs wafer with one surface metallized to form a common LED contact. Epitaxially formed on this wafer is a GaAs/GaAlAs heterostructure with successive layers of Ga.sub.1-x Al.sub.x As-n, GaAs-p, and Ga.sub.1-y Al.sub.y As-p on the other surface, followed by an electrical contact layer of GaAs-p+ and an insulating layer of SiO.sub.2, discrete areas of the contact and insulating layers being removed by etching to form viewing windows for the individual LEDs, and with the area of the contact layer bordering the viewing windows being exposed and metallized to provide individual LED electrical contacts.In a second embodiment, the GaAs-p+ layer is dispensed with and the transparent electrically conducting coating is applied directly on both the insulating layer bordering the Ga.sub.1-y Al.sub.y As viewing windows and over the viewing windows.
Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.
April 13, 1984
Date of Patent:
February 3, 1987
Fairchild Camera & Instrument Corp.
Michael E. Thomas, Madhukar B. Vora, Ashok K. Kapoor
Abstract: A method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor. An external lead of a lead frame extends to one side of a substrate support serving as a heat sink and supporting a semiconductor substrate, and strips of the lead frame extend to the other end of the substrate support. The external lead and strips are clamped by upper and lower molds for plastic encapsulation so that a thin film of plastic is uniformly formed on a lower surface of the substrate support. A connecting portion between the external lead and a connecting band and the strips extending from a plastic encapsulating housing to the outside are cut.