Abstract: In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.

Abstract: A system and method for synchronizing mirrored and striped disk writes. A data storage system may include a client computer system coupled to a first data storage device and a second data storage device and configured to transmit a first data write request. The first storage device may be configured to transmit a sequence number to the client computer system in response to receiving the first data write request. The client computer system may be further configured to transmit a second data write request including the sequence number to the second storage device. The second data storage device may include a counter and is configured to compare a current counter value to the sequence number. If the counter value is equal to the sequence number, the second storage device stores the data bytes corresponding to the second data write request and increments its counter.

Abstract: The invention provides a system and method for tracking memory information associated with dynamically loaded kernel modules with the help of a tracking system. The tracking system defines its own kernel memory allocation functions. Whenever, a dynamic kernel module is loaded/unloaded into/from the kernel space, these newly defined functions are called in response to kernel memory allocation/de-allocation requests from the kernel module. The newly defined functions are responsible for allocating and de-allocating kernel memory, as well as, keeping track of information relating to the kernel memory allocations/de-allocations. The tracked information may be used to identify the source of kernel memory leaks.

Abstract: Disclosed herein is a data recording apparatus which may include a recording data acquisition section, a data recording section, a file management section, a recording control section, and a file updating control section.

Abstract: A storage apparatus is proposed for facilitating wireless communication between a computer device and one or more external portable electronic devices, or between those external devices. The storage apparatus includes a wireless transceiver for entering communication with any of one the devices. When the storage apparatus is communicating with any of the devices, it can transmit to that device any data stored in its memory for transmission to that device. Furthermore, the storage apparatus can receive from that device, and transmit to its memory, data to be relayed to another of the devices.

Abstract: A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

Abstract: A fault-tolerant and efficient way of deducing a set of inconsistent stripes for a network RAID protocol, wherein clients forward input/output (I/O) to a particular controller device called the coordinator, which executes RAID logic and which sends out device IOs to the relevant storage devices. If the coordinator fails then a new coordinator reconstructs its state from the storage devices.

Abstract: A cache memory device comprises a secondary tag RAM that partially constitutes a secondary cache memory and employs a set associative scheme having a plurality of ways, and a secondary cache access controller that, when the number of ways in the secondary tag RAM is changed, allocates tags to respective entries so that the total number of entries constituting the secondary tag RAM and the total number of entries after the number of ways is changed are constant.

Abstract: There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.