Abstract: A method for preventing thermal stress and the shifting of alignment marks during semiconductor processing including providing a semiconductor wafer having a first selected portion for fabricating integrated circuitry and a second non-fabrication portion including alignment marks, introducing dopant into said first and second portions, when dopant is required to be introduced in said first portion, thereby increasing radiant energy absorptivity and decreasing radiant energy transmissivity in both portions such that the thermal emissions detected.at the portions result in no significant temperature variation between portions during heating. Therefore thermal stress and shifting of alignment marks are prevented.