Abstract: A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

Abstract: A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.

Abstract: A storage processor is interposed between initiators and storage targets, such as storage appliances or storage devices in a storage network. The storage processor presents a target interface to the initiators and an initiator interface to the targets, and the storage processor transparently intercepts and processes commands, data and/or status information (such as iSCSI R2T and data PDUs) sent between the initiators and the targets. The storage processor presents a virtual device to the initiators and transparently implements the virtual device on the targets, such as a RAID-1. The storage processor negotiates acceptable operational parameters, such as maximum segment size, with the initiators and targets, such that the storage processor can pass data received from the initiators to the targets, without excessive data buffering.

Abstract: A method and apparatus are provided for allowing a UPnP control point to recognize various entities. The method includes: generating a device description describing information on the entity in a format according to the standard using the information on the entity; and presenting a role of the device supporting the standard for a control point, which can recognize only devices supporting the standard, based on the generated device description. Accordingly, UPnP can be applied to various entities.

Abstract: The present invention is directed towards reducing hard disk drive (HDD) activity by sharing the buffering activity between a provisional load sharing buffer (PLSB) and a time shift buffer (TSB). The HDD may be included in a digital host communications terminal (DHCT). Initially, the PLSB buffers initial streaming programs to accommodate for channel changes. Additionally, the streaming program is buffered in a standard definition quality regardless of the format of a connected television. Once a predetermined time has passed determined by the size of the PLSB without a channel change, the TSB begins buffering the streaming program. The TSB can then switch between buffering a high definition quality to a standard definition quality of a streaming high definition program depending on other factors to further decrease the HDD activity. Additionally, the TSB can be disabled to prevent buffering of the streaming program.

Abstract: The present invention provides a method for releasing data of a storage apparatus. The method manages the data output of the storage apparatus by using a virtual output queue, a data storing memory, and a bit map output port memory. In such method, the output ports, which use the data stored in any data column of the data storing memory, are recorded in the bit map output port memory. In addition, the addresses of the data storing memory for storing the data output from any output port are provided by the virtual output queue. After all data of a certain data column is completed read out, the data storing column in the data storing memory and a corresponding part of the bit map output port memory are released by the storage apparatus.

Abstract: A computer program product and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation.

Abstract: Assigning addresses to legacy sharing at least one signal line with a plurality of client devices. Each of the devices includes a number of I/O pins selected ones of which are connected to the at least one signal line and each client device includes a first and a second initialization pin. In the described embodiment, all but a first one of the plurality of client devices are connected to one another in a daisy chain arrangement by way of the first and the second initialization pin separate from the signal line. A first client device has a first initialization pin that is independently held at a first logic level and a second initialization pin that is connected to the daisy chain arrangement. The first one of the client devices is initialized and, in turn, triggers initialization of the daisy chained client devices. The legacy device is initialized separately from the client devices.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: A method comprises providing a free buffer pool in a memory including a non-negative number of free buffers that are not allocated to a queue for buffering data. A request is received to add one of the free buffers to the queue. One of the free buffers is allocated to the queue in response to the request, if the queue has fewer than a first predetermined number of buffers associated with a session type of the queue. One of the free buffers is allocated to the queue, if a number of buffers in the queue is at least as large as the first predetermined number and less than a second predetermined number associated with the session type, and the number of free buffers is greater than zero.

Abstract: A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.

Abstract: A reordering command queue for reordering memory accesses in a computer system. The reordering command queue may reduce the power that is typically used up in computer systems when performing accesses to main memory by improving the scheduling of memory accesses with a pattern that is optimized for power and which has no (or negligible) impacting on performance. During a compare operation, the address corresponding to the command stored in each of one or more current storage locations of the reordering command queue may be compared to the address corresponding to the command stored in an adjacent storage location to determine whether the commands are in a desired order. In response to one or more of the commands not being in the desired order, a reordering operation may be performed, which may reorder each of the one or more commands from a current storage location to the adjacent storage location.

Abstract: A storage control apparatus of the present invention controls the number of multiple commands issued from a host machine without shutting down the host machine. A communication port of the storage control apparatus carries out communications with the hosts in accordance with the iSCSI protocol. Command processing resources are managed for each communication port. A resource allocation control part calculates the number of commands capable of being received on the basis of the remaining amount of command processing resources inside shared port resources, a change in the number of commands received from a host, communication delay time, and the state of execution of a command issued from a host or the like. A MaxCmdSN is calculated by adding the results of command processing by a command execution part and the receivable number calculated by the resource allocation control part to the value of the latest CmdSN received from a host.

Abstract: A fault-tolerant computer is capable of performing a data flow control process in a short period of time. The fault-tolerant computer includes a pair of duplicate systems each having a CPU subsystem and an IO subsystem. The IO subsystems of the duplicate systems are connected to each other through a cross link. The CPU system has an inbound reception buffer which receives data sent from the IO subsystem, and when the amount of the received data reaches a first threshold value, sends a first signal to the IO subsystem, and when the amount of the received data reaches a second threshold value greater than the first threshold value, sends a second signal to the IO subsystem. The IO subsystem has an IO I/F controller to stop sending data to the CPU subsystem when the IO I/F controller receives the first signal and the second signal, and a flow controller to send the second signal to the IO I/F controller of the paired IO subsystem through the cross link after the flow controller receives the second signal.

Abstract: A robust device messaging framework is disclosed that enables a user to send commands to a device. A provisioning service is used to provision unique device identities and maps user web identities to device identities. The provisioning service also limits device per day provisioning attempts to limit denial of service attacks. A command service allows remote users to issue commands to a device, synchronize outgoing commands with incoming results, receive accurate feedback about whether a command was received, and maintain state information about the device. A device layer encrypts and stores device identities, authenticates itself with the command service, establishes a high-availability Internet connection to receive alerts that a command has issued, and reports results to the server-based command service.

Abstract: The present invention provides a method for automatically executing files in a semiconductor storage device. In this method, a specific file in the semiconductor storage device coupled to a host computer is automatically executed by activating the AutoRun mechanism of the operation system. The storage function of the semiconductor storage device is combined with the AutoRun function of files of the operation system according to the present invention. The method is applicable to various operation systems, and broadens the application function of the semiconductor storage device.

Abstract: Memory resources can be optimized by dynamically determining a threshold value of a storage device used for buffering in accordance with a compression rate of data for streaming reproduction. A data reproduction device for temporarily storing compressed data that is downloaded from a server and sequentially performing the streaming reproduction, wherein the amount of data stored in a HDD is optimized by changing and setting the threshold value in accordance with the compression rate of the compressed data.

Abstract: Systems and methods for controlling the rise and fall times of USB signals for USB devices and peripherals are provided. The rise and fall times of USB peripherals can be controlled, or changed, in order to match the electrical characteristics of the USB peripheral to a USB host. By sweeping through a range of rise and fall times, and testing the reliability of USB output, optimal rise and fall times for the characteristics of a USB peripheral can quickly be determined. In one embodiment, the controllability of the rise and fall times is provided in firmware that changes at least one characteristic of the USB peripheral that affects the amount of current flowing during USB signaling.

Abstract: A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream. A first-in first-out buffer passes data from the stream between the data producing process and the data consuming process. The buffer comprises buffer memory, the buffer writes data-items from the stream in circular fashion into the buffer memory. A consuming process interface is arranged to process a command for making a data grain from the stream available to the data consuming process. The interface responds to the command by testing whether addresses of data within the grain to which access has to be gained wrap around in the circular FIFO buffer.

Abstract: Embedding endianness information within data and sending and receiving data with the embedded endianness information. Data may be contained in a data structure. To embed endianness information in a data structure, unused bits in a data structure are identified. A number of the unused bits are then selected based on the possible unpacking combinations of the data structure. The endian bit values are set to a pattern to indicate the endianness of the data structure. Data that has been packed by a transmitting module can be unpacked by a receiving module based on the detected endian bits. An algorithm may be used to determine which unused bits to select as the endian bits.