Abstract: A process and system for flushing high-speed buffers in a serial link used between a mover circuit (4) that executes data move operations and at least two memories through at least two channels (400, 401), the data move operations each being constituted by a move request followed by the return of a response or acknowledgement of the request, cyclically with interlacing, the responses following the same pair of serial channels (400, 401) as the requests for which they constitute the acknowledgements. The process comprises:a step for placing the mover circuit (4) into a so-called "absorption" mode of operation,a step for generating a specific write request and a specific read request, each of which comprises a so-called "barrier" marker contained in a control character preceding or following the request,a step for accumulating the responses received, anda step for comparing the responses received.

Abstract: A method and apparatus for reconfiguring a file or logical volume stored on a magnetic disk storage system for optimal performance. The magnetic disk storage system contains a cache volume constituted as free storage. When appropriate, a file can be copied from its normal storage location to the cache volume with a different format to optimize the file for subsequent operations. After such operations are complete, the file can be transferred from the cache volume back to the normal storage location in the original format.

Abstract: A processor used in a synchronous data transfer system in which a processor, a direct memory access controller and peripheral devices are connected to a memory via the same bus, includes a detection circuit for detecting whether the processor uses the bus in a forthcoming cycle, and a control circuit having a first terminal for acknowledging a request signal from the direct memory access controller requesting a use of the bus, only when the detection circuit detects that the processor does not use the bus in the forthcoming cycle, wherein the control circuit discards a right to use the bus and outputs a response signal to the direct memory access controller indicating that the processor grants the right to use the bus to the direct memory access controller, when the request signal is acknowledged.

Abstract: A method and apparatus for handling outgoing communication requests in an information handling system in which outgoing communication packets are accumulated into a block that is written to an input/output (I/O) device. For each I/O device there is generated a blocking factor representing a predetermined number of packets that are accumulated before the block is written to the I/O device, as well as a push interval representing a maximum period of time for which any packet in the block can be stalled. Upon the arrival of a new outgoing packet, the packet is added to the block, and the block is written to the I/O device if either the block now contains the predetermined packets or any packet in the packet has been waiting for more than the push interval. A timer running asynchronously with the arrival of outgoing requests periodically pops to write the block to the I/O device if it has been waiting overlong, even if no new requests have arrived.

Abstract: A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that comprises a bank of 32k word RAM, six dual port 16-word FIFOs, and associated sequencing logic. The sequencing logic includes RAM address registers/counter associated with each of the six FIFOs, and manages the movement of data into and out of the RAM.

Abstract: A data input-output device includes a single memory, an input interface unit for storing data in the memory, an operation unit for fetching the data from the memory, for performing operations on the data, and for updating the data in the memory when necessary, an output interface unit for transmitting the data in the memory that has been operated on by the operation unit to outside of the device, and a bus control unit for setting a priority for each of these units and for controlling memory access by these units according to the priorities every time a predetermined number of bytes of data is transferred.