Abstract: A cascaded apparatus of graphic processors for cascading a main graphic processor and at least one secondary graphic processor comprising a clock generator for generating the clock signal to control the timing and synchronize the all the actions; a pixel synchronizer for synchronizing the color codes and layer codes; a layer comparator for comparing the level of layer codes; a mode selector for selecting the mode; a cascade controller for comparing the layer and outputting the color codes; and a color code output device which determines the output of color codes.