Abstract: An interface connector device for interconnecting a plurality of input/output devices including a signal bus connected to a control and to the input/output devices for multiplexing the signals between the control and the input and output devices, the bus interconnecting a plurality of interface and connector devices, and each of the interface and connector devices including address recognition circuitry as well as programmable configuration selection logic to configure the connector device to respond to a variety of input/output devices. In addition, the signal bus and connector devices are adapted to recognize and convey various levels of signals, for example, different voltage levels representing control information, framing signals, and diagnostic command signals.

Abstract: Thin-film circuits comprising e.g. TFTs have inferior performance as compared with monolithic integrated circuits, and this inferior performance limits their use for e.g. drive circuits in large-area electronic devices such as an active matrix liquid-crystal display. In accordance with the invention, feedback with an external amplifier (150) is used to enhance the performance of a thin-film circuit. The feedback is taken from parallel nodes (40) of sequential stages (T1) of the circuit so that a common feedback line (51) and common external amplifier (150) can be used, thus reducing the number of substrate terminals and external connections required. Various buffers may be included between the feedback line (51) and the feedback terminal (56) to reduce the capacitive load on the line (51).

Abstract: Method and apparatus for providing gray level addressing for passive liquid crystal display (LCD) panels having overlapping row and column electrodes defining pixels are disclosed. Depending upon whether the rows are being addressed by "standard" or "Swift" addressing, the signals for applying to the column electrodes are determined by different calculations, in all of which modes the amplitudes of the column signals are related to the gray level desired to be displayed by the individual pixels. For a split interval system, column signals of appropriate amplitude and polarity are applied during different subintervals of a characteristic time interval of the display panel depending upon the method of addressing the rows. In the full interval mode, the column signals applied over a full time interval are based on the desired gray level of all the pixels in the column, adjusted to provide the proper rms voltage across all the pixels so that they display the desired gray levels.

Abstract: The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grid is coupled by a link to a bus having a predetermined voltage. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.

Abstract: An image processing apparatus especially suitable for image processing operations such as enlarging, reducing, rotating and scrolling avoids use of a second video memory. The image processing device comprises a memory having memory elements for storing picture element data of a video information which describes an original image, an operation circuit for receiving a start address where a read operation is to start within the memory and a predetermined data indicative of a difference between the start address and a next address where the read operation is to be made, and for calculating the next address from the start address data and the predetermined data, a reading circuit for reading the picture element data which is stored in the memory at the next address calculated by the operation circuit, and an output circuit for outputting the picture element data read by the reading circuit.

Abstract: A video game controller, for inputting command signals to a game port having a finite number of discrete and analog signal inputs, provides a plurality of additional discrete outputs multiplexed on one of the analog outputs. This controller has a plurality of parallel switches each coupled to the one analog output via a different value resistance. Circuitry in the game board in combination with programming in the video game or simulation software recognizes discrete voltage levels input from the controller via the one analog port as different discrete commands. This enables the range of commands that can be input from a video game controller to be substantially increased without making any change to the base computer hardware.

Abstract: An image data processing system is disclosed which includes an image data receiving element, e.g., a CCD module, for receiving and converting a plurality of image data into electrical signals. The image data processing system further includes a color processing subsystem which includes the color separation unit, the RGB generation unit, the white balance control unit, the gamma correction unit, and the color space converter, for processing the electrical signals for generating color display output representing the color space of the image data. The image data processing system further includes a luminance processing units which includes two 1-H line memory units, the low pass filter, the edge enhancement unit, the summing circuit and the gamma correction unit, for filtering and processing the electrical signals for generating luminance output representing the luminance field of the image data.

Abstract: A method and apparatus for the storage and retrieval of pixel information, including first and second data portions, is shown to include first and second memory devices each having a random access memory and a shift register, wherein the random access memory includes an on screen section and an off screen section. Pixel information is retrieved from the random access memories in response to control signals and transferred to the shift registers. A controller controls the storage and retrieval of the first data portion in the on screen section of the first memory device, controls the storage and retrieval of the second data portion in the off screen section of the second memory device and generates the control signals so that the first and second data portions are outputted from the shift registers simultaneously.

Abstract: An apparatus having dual modes and adapted to control a position of a cursor on a display screen comprises a ball capable of being put in a rotation for determining the position, a roller device in contact with the ball to detect the rotation of the ball, a shell having thereon an opening to protrude therefrom the ball and accommodating therein the ball and the roller device, and a cover mounted on and connected to the shell, extractable therefrom to shield the ball from being inadvertently contacted, and retractable to be received therein to permit the apparatus to be normally used. This invention provides a simple apparatus capable of functioning as either a track ball or a mouse used for controlling a cursor on a display screen, e.g. a monitor.

Abstract: A memory apparatus for use in a receiver for decoding video signals comprises a first memory for storing an image frame; a second memory for storing current pixel data temporally and providing the same to said first memory; an address generator for generating address signals for sequentially addressing two-dimensional pixels in the blocks; a delay unit for delaying said address signals by a predetermined delay time in generating write address signals for said first memory; an offset unit for comparing the said address signals with an offset address so as to prohibit the provision of write address signals to said first memory until one of said address signals reaches to said offset address; and a control circuit for selectively providing the read address signals and the write address signals to said first memory.

Abstract: An active-matrix type LCD includes a plurality of gate bus lines and a plurality of drain bus lines each intersecting with a corresponding gate bus line at right angle, and a liquid crystal provided between a substrate on which a TFT is formed at the intersection of the gate bus line and drain bus line, and a substrate on which a common electrode is formed. The active-matrix type LCD further includes a device for producing a compensation signal to compensate a source electrode voltage of the TFT for each divided section of the display area of the active-matrix type LCD, the each divided section being obtained by dividing the display area into a plurality of sections for exposure to light when a pattern of the electrode is formed, and an adder circuit for adding the compensation signal and associated image signal, and producing the added signal.

Abstract: A transmitting-receiving unit or a set of upper rank transmitting-receiving units and lower rank transmitting-receiving units are provided, and one or a plurality of circuits selected by a circuit selective switch unit from among many circuits are connected to the transmitting-receiving unit or the set. As a result, the burden of the control unit provided in the communication device is reduced. The maintenance of a route table which is used in transmitting packets from the highest rank station to the lowest rank station via other communication devices is made unnecessary by transferring the route table in order from the highest rank stations to the lowest rank stations.

Abstract: In a video editing apparatus, picture-representing data are stored in an area of a RAM, with a section of the data being selected to be transferred to form a display picture. When a command is supplied for cutting-out a region of the display picture, to replace the cut-out region with other data, the corresponding data region of the RAM area is stored in memory. If the user subsequently designates that the original data of the cut-out region are to be temporarily replaced in the display picture, the position of the cut-out region is calculated with respect to the data region that is currently being selected from the RAM area, the position with respect to the display picture is thereby obtained, and the cut-out data region is then read out of memory and inserted into the display picture at the obtained position.

Abstract: A flat panel color display is provided in which white collimated light incident on a light coupling means having a metal layer and a liquid crystal layer formed on a surface of the coupling means produces a colored spot of light at the interface of the metal layer and liquid crystal layer through the excitation of surface plasmons. The present invention utilizes the color selective scattering of incident white light by surface plasmons and includes a coupling device, such as a high index glass prism, with a metal film layer and a liquid crystal layer formed on the coupling device. Surface plasmon waves can be generated at a negative dielectric (metal layer)-positive dielectric (liquid crystal layer) interface when the dispersion relationship is satisfied. The incident white light includes photons which have frequencies approximately equal to the plasmon resonance, and such photons are strongly scattered. Photons having a frequency other than the plasmon resonance will be totally reflected.

Abstract: A home computer system having a single input-output which is modified by a identifying circuit to identify a joystick or a mouse the identifying circuit utilizes potentiometers from the joystick which are connected to monostable circuits. The computer automatically recognizes that a joystick is present due to the triggering of the monostable circuits and the reading of the outputs from those monostable circuits.

Abstract: A digital still store system (10) receives composite digital 4:2:2 D1 video signal inputs in parallel at (12) or serially at (14). The signals are supplied in component form selectively to one of framestores (18) and (20). The component signals are supplied from the framestores (18) and (20) to hard disks (22) through a buffer store (24) and disk input/output (I/O) circuits (26). Each of the hard disks (22) stores still video images as either 525 or 625 line digital frames for either NTSC or PAL composite signal inputs and outputs. Y and C fields of component video signal information are supplied from the hard disks (22) through the buffer store (24) and one of the frame stores 18 and 20 to a compositor (28) for output as digital 4:2:2 video signals. The buffer store (24) obtains the video signal fields for either full size images or 1/4 size images, when an array for browsing and selection is desired.

Abstract: A self-scanning light-emitting element array is disclosed. A coupled array of light-emitting elements is constituted so that a light-emitting element which is turned on influences a light-emitting element to be turned on next so that its threshold level is changed. When each element is clock-driven by a common drive pulse, the change in threshold level is shifted in the array direction, so that a turn-on operation is transferred in a clock period of the drive pulse.

Abstract: Each display control block processes color pixel data stored in a refresh memory to convert the processed data into 1-bit monochromatic picture signals. At this time, the color information possessed by the respective color pixel data are converted in a form in which the color information possessed by the color pixel data may be expressed on a monochromatic display panel. The monochromatic picture signals produced by plural display control blocks are synthesized in a display synthesizing circuit and converted into one monochromatic picture signal. At this time, the display synthesizing circuit synthesizes the signals with different degrees of display preference so that the picture surface having a lower display preference is not seen on the picture surface having a higher display preference.

Abstract: In a character generating method and apparatus for producing a bit map image of a designated character size from outline data, a character developing circuit calculates a shearing factor of a target stroke when a conversion scaling factor is smaller than a predetermined scaling factor, performs shearing compensation on coordinates of individual points of the target stroke along a coordinate axis according to a type of the target stroke, based on the shearing factor, and converts outline coordinate data obtained through the shearing compensation, to physical coordinates, for the designated size based on the conversion scaling factor. A drawing circuit produces a bit map image of the designated character size from the converted physical coordinates. The character generating apparatus further has a font memory for storing the outline data.

Abstract: This invention provides a driving apparatus for a liquid-crystal display, comprising a dot-matrix liquid-crystal display with column electrodes and row electrodes, a control circuit for, in enlarging and displaying the display data, producing a display control signal containing a plurality of pulses during the latch period of a latch signal that latches the display data, a column-electrode driving section for latching the display data in a latch circuit in response to the display control signal from the control circuit, and based on the latched display data, causing a driving circuit to drive the column electrodes of the liquid-crystal display, and a row-electrode driving section for simultaneously driving a plurality of adjacent row electrodes of the liquid-crystal display in response to the display control signal from the control circuit.