Abstract: The invention is a relay communications system which uses a single reference frequency signal generator to produce a plurality of precisely frequency synchronized code division multiple access radio frequency signals. A transmitter transmits the synchronized signals to a remote satellite based retransmitter which includes a slave oscillator precisely synchronized to the reference signal generator for down-linking the multiple radio frequency signals to a common radio frequency with all of the down-linked signals being in precise phase synchronism. The relative phase of the down-linked signals can be preserved or altered and the signals combined and amplified by a high-power amplifier operating in the saturation mode. The output from the high power amplifier is applied to a beamforming network to form an overlapping beam signal comprised of multiple code division multiple access information signals.
December 1, 1989
Date of Patent:
August 6, 1991
Hughes Aircraft Company
Arnold L. Berman, Gilles G. du Bellay, Marvin R. Wachs
Abstract: A communications network is comprised of master and slave stations. The master stations may receive a master token allowing control of the network for sending messages, and a solicit token that allowing the master stations to solicit other master stations for entry into the network. A master station receiving a solicit message answers with an acknowledgement signal and may immediately begin soliciting for successors. The slave stations receiving a solicit message may not accept the master token or the solicit token but must respond with a negative acknowledgement. Slave stations enter the network to respond to messages only. The use of slave stations allows for the implementation of simpler networks and improves network efficiency. The negative acknowledgement identifies the presence of the slave stations and allows detection of duplicate network nodes.
Abstract: A synchronizer in a receiver for a serial data stream includes a shift register for temporarily storing the most recently received data. Taps at a plurality of locations on such shift register provide bit signals at regularly spaced locations. These bit signals are checked for the occurrence of predetermined patterns which indicate the occurrence of frame bit candidates. A candidate shift register indicates which bit positions currently remain as candidates for the frame bit position, and is shifted synchronously with the incoming data. The candidate shift register is N bits in length, and a modulo-N counter is connected to the serial output thereof. Each time a bit position shifted out of the candidate register contains a valid candidate, the modulo-N counter is reset. When the counter counts for a full cycle, the true frame bit position has been identified.
Abstract: The flow of data cells through a transmission medium with a plurality of virtual, asynchronously time-divided transmission channels is protected against excessive crowding of data cells in any channel, or of any customer, by means of a counter for each channel and the recording of the time or arrival of data cells in each channel. The counter is advanced by a predetermined amount at the arrival of each data cell and in the same operation is decreased by a value which is a function of the length of time between the moment of arrival of that data cell and the moment of arrival of a preceding data cell with the same channel designation. The state of the counter is also compared with a threshold value which, if equalled or exceeded results in the data cell not being switched through a switch controlled by the comparison, while in other cases the data cell is let through to the downstream portion of the channel.
January 30, 1990
Date of Patent:
April 9, 1991
Koninklijke PTT Nederland N.V.
Frans van den Dool, Jacob C. van der Wal
Abstract: A synchronizer in a receiver for a serial data stream includes a shift register for temporarily storing the most recently received data. Taps at a plurality of locations on such shift register provide bit signals at regularly spaced locations. A cyclic shift register is clocked each time a true frame bit is received. Combinational logic connected to the data taps determines whether a pattern indicating a possible multiframe alignment exists at the data taps. Multiframe candidates are stored in the cycle shift register until all but one are eliminated, with the remaining candidate indicating multiframe alignment.
Abstract: A multi-point conference system for making a video conference includes a center unit having a controller and an image selector, and three or more stations respectively coupled to the center unit, where each station includes at least one camera for picking up an image to output an image data, a display for displaying an image based on an image data and a request part for making a request. The controller initially sets master, sub and participating stations in conformance with a predetermined rule. The image selector automatically supplies the image data from the master station to the sub and participating stations to be displayed on the display thereof and supplies the image data from the sub station to the master station to be displayed on the display thereof.
Abstract: Improved throughput is realized in a packet cross-connect switch by including an addressable memory unit in each of a plurality of input ports for storing packets and by allowing each of a plurality of output ports to address directly any one of the input ports to obtain a particular packet stored therein, which is destined for the output port. To this end, the input ports supply the packet destination and starting address of the packet stored in their memory to a scheduler. The scheduler controllably selects an output port assigned to the packet destination and supplies packet output information to the selected output port including the packet starting address and the identity of the input port storing the packet. When a particular output port is ready to obtain a particular packet, it addresses the memory unit in the particular input port to read the first packet word. The addressed packet word is supplied via a data bus to the requesting output port.
Abstract: A packet switching arrangement for receiving packets including broadcast addresses and connecting representations of the received packets to any combination of output ports specified in the address is disclosed. The packet routing units of the network both generate packet representations and selectively connect the representations to downstream routing units or network outputs. Packets for use with the network comprise an address portion encoded in a broadcast format or in a shorter point-to-point format and an address type character identifying the type of address in the address portion. The nodes of the network respond to the address type character of a received packet. By selecting the appropriate decoding format for the packet address portion, a packet select unit decodes the address portion in accordance with the selected encoding format and selectively connects the packet to the network outputs.
Abstract: A method for performing a duplicated address test used for a network including a first ring transmission line, a second ring transmission line having a signal transmission direction opposite to that of the first ring transmission line, and a plurality of stations connected to at least one of these ring transmission lines. Each of these stations has a flag DAC representing whether or not the duplicated address test is performed, and some of the plural stations constitute a plurality of control nodes having a configuration function of the network. The flag DAC of each of the stations is reset at a time instant when a power source of this station is turned on, and also when any of the control nodes receives the sent out configuration control frame. Each of the stations having the reset flags DAC sents out the duplicated address test frame to either the first or second transmission line to which the station is connected when a token frame to control a transmission right is captured.