Abstract: A semiconductor device that operates at high speed using a low voltage power source, in which the output of each gate in the standby state is stable, and which has a delay time that is not affected by the frequency of the input signal. TrQ1 to TrQ8, which form multiple stages of the inverters are designed to have a low threshold voltage in order to accomplish low voltage operation. When input node A is at “L” in the standby state, TrQ2, Q3, Q6, and Q8 which cut-off are connected to high threshold voltage TrQn1 and Qp1. In the standby state, power cutting TrQn1 and Qp1 cut off in accordance with chip selecting signals CS, /CS, thereby blocking the flow of sub-threshold current to TrQ1˜Q8. Since TrQ1, Q4, Q5 and Q8 are not cut off at this time, the output potential of each inverter is stable.