Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable pads to one of the MCM's reference voltage pins. By applying a supply voltage to the test mode enable pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a reference voltage applied to the test mode enable pads through the reference voltage pins and the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: In order to obtain a flip-flop circuit which reduces an S/H time or a T-Q delay while suppressing power consumption, a master latch is formed by a dynamic half latch having a transmission gate (S1) and an invertor (INV1), while a slave latch is formed by a static half latch having transmission gates (S3, S4) and invertors (INV3, INV4). In the slave latch, the operation of the transmission gate (S4) is controlled not only by a clock signal (T) but by a mode signal (MODE). When the mode signal (MODE) is converted to a low level, the transmission gate (S4) enters a nonconducting state, so that the slave latch performs a dynamic operation.

Abstract: The invention relates to a measuring apparatus used for testing the connections between at least two subassemblies (3, 4, 5), comprising a test system (1) for generating a test signal available on an output of the test system and for evaluating an analysis signal produced by a subassembly (3, 4, 5) from the test signal and received on an input of the test system. The test system (1) is also provided for applying a switch control signal to a controller (10, 11, 12) included in a subassembly (3, 4, 5). A subassembly (3, 4, 5) includes a switching circuit (7, 8, 9) controlled by the assigned controller (10, 11, 12), which switching circuit is provided for directing a test signal or an intermediate signal formed from this test signal to a test input of a subassembly and for receiving at least a further intermediate signal from a test output of a subassembly.