Abstract: A counterbalance apparatus for use in a workstation to raise and lower a work surface of the workstation. The counterbalance apparatus compensates for the load on the work surface. The counterbalance apparatus includes an inner column telescopingly mounted in an outer column. A base member is positioned at one end of the outer column. A grooved member positioned between the inner column and the base member and a force mechanism between the grooved member and the inner column or the work surface. The grooved member moves in and out of the inner column and base member to raise and lower the work surface.

Abstract: Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.

Abstract: A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circu

Abstract: A receiver for bidirectional signal transmission, where signals are sent and received in both directions over a signal transmission line, has a signal line, a first hold capacitor, a signal line voltage buffer circuit, a hybrid circuit, and a decision circuit. The signal line is connected to the signal transmission line, the first hold capacitor is used to hold a signal, and the signal line voltage buffer circuit is used to buffer a voltage of the signal line. Further, the hybrid circuit is used to output a received signal by separating the received signal from the signal line voltage buffered by the buffer circuit, and the decision circuit is used to make a decision on the logic value of the received signal separated and output by the hybrid circuit.

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Abstract: A logic element for a programmable logic device (PLD) can be configured as a shift register of variable length. An array of memory cells in the logic element is divided into two or more portions. The memory cells of each portion supply values to a corresponding output multiplexing circuit, thereby enabling the logic element to function as a lookup table by combining the outputs of the multiplexing circuits. However, each portion is also configurable as a shift register. The portions can function as separate shift registers, or can be concatenated to function as a single shift register. In some embodiments, the portions can also be concatenated with shift registers in other logic elements. Because two or more output multiplexing circuits are available, two or more taps are provided, one from each portion of the memory array.

Abstract: An active resistor design is adapted to implement a linearized transistor driver that includes a first FET coupled between a supply potential and an output node, with the gate of the first FET being coupled to an input node. Second and third FETs are coupled between the output node and a reference potential, with the gate of the second FET being coupled to the input node.

Abstract: A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps. A set of package routing leads is positioned between the grid of signal interface bumps and the solder ball.

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: A mixed signal codec includes: a multiplexer amplifier 24 having an analog output signal; a sigma-delta analog to digital converter 26 having an input coupled to the analog output signal; and a clipping circuit 40 and 42 coupled to the input of the analog to digital converter for clipping the analog output signal.

Abstract: A product-term array that may allow for the implementation of product terms requiring less silicon area than conventional designs. The product terms may also have a shorter propagation delay when compared with conventional designs. A multiplexer, which may be programmed with a configuration bit or signal, may select the polarity of an input signal to the product-term array. Duplicating a number of the initial inputs to the array may accommodate particular design constraints that may require both polarities (i.e., both positive and negative) of a given signal or set of signals. Even with the duplication of certain inputs, the total number of product-term inputs to the array will generally be reduced when compared with conventional designs, that duplicate the polarity of every input internally to the array.

Abstract: A signal processor for 1-bit signals comprises an nth order D Sigma Modulator (DSM) having an input (4) for receiving a 1-bit signal and an output (5) at which a processed 1-bit signal is produced by a quantizer (Q). The quantizer (Q) receives a p-bit signal from a series of 5 signal integration stages. Each stage comprises a first 1-bit multiplier (An) coupled to the input (4), a second 1-bit multiplier (Cn) coupled to the output (5), an adder (6n) which sums the outputs of the coefficient multipliers and an integrator (7n) which integrates the output of the adder (6n). A final stage comprises a coefficient multiplier (An+1) and an adder (6n+1). The adder (6n+1) sums the output of the coefficient multiplier (An+1) and the output of the integrator of the preceding integration stage. The input signal is fed to all the stages except the final stage via a 1-bit delay. The output signal of the quantizer is fed back to the stages via a 1-bit delay.

Abstract: An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer.

Abstract: The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal.

Abstract: A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

Abstract: The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting circuit path and the inverting circuit path preferably are of identical construction and each contain at least one neuron transistor (NT1, NT1'). The corresponding neuron transistor gates in the non-inverting circuit path and in the inverting circuit path are driven inversely with respect to one another.

Abstract: A plurality of light-receiving devices dispersed over the area of an IC chip operate in response to the opening of an IC device such that switching transistors are turned on or off to prohibit the normal operation of logic circuits or logic elements, thereby securing protection against normal reading of the internal data of the opened IC device, particularly against the analysis of the IC's internal logic with an electron beam tester.

Abstract: An output buffer to serve as an interface between a main logic circuit and a peripheral device is described. The output buffer includes a first transistor adapted to be coupled to a first voltage supply and an output terminal. The first transistor is designed to charge the output terminal to a first state. A pull-down network to charge the output terminal to a second state is also included. The pull-down network is adapted to be coupled between the output terminal and a second voltage supply and is designed for alternate operation with the first transistor. The output buffer also includes a logic circuit to enable the first transistor and the pull-down network. The logic circuit is coupled to an enable terminal of the first transistor, the pull-down network, the first voltage supply, and the second voltage supply.