Patents Examined by V. Yevskiov
  • Patent number: 6617208
    Abstract: The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75 to form an integrated circuit capacitor. One metal plate 40 is copper formed using a damascene process. The high capacitance of the structure is due to the thin high k dielectric material used to form the etch-stop/capacitor dielectric layer 60.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: September 9, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Mukul Saran