Abstract: A lateral pnp transistor for use in programmable logic arrays. The lateral pnp has a layer of oxide disposed between a polysilicon layer and the base along the base width. The oxide layer prevents diffusion of the N+ dopant contained in the polysilicon layer into the N- base region. The base region thus remains N- and the resulting transistor has improved breakdown voltage characteristics while retaining the speed advantages of polysilicon contact layers. The lateral pnp transistor is manufactured by a method which requires minimal deviation from other methods used to manufacture lateral pnp transistors.

Abstract: Both homojunction and heterojunction bipolar transistor structures are fabricated in unique trenched configurations so as to better utilize their surface areas by employing both the vertical and horizontal portions of their base regions with equal effectiveness. An important advantage of the unique trenched configurations is that the base region of each trenched structure is of precisely the same thickness throughout--both vertical and horizontal portions. Consequently, the transit time for charge carriers to diffuse across the base region and the base transport factor are uniform because of the uniform base thickness. Moreover, the parasitic capacitance region of each trenched structure beneath base metallization contacts is only a small portion of the entire base-collector junction region.

Abstract: Disclosed herein is a diamond Schottky gate type field effect transistor (FET) comprising: an insulating diamond under layer; a doped semiconducting diamond layer as an active layer, which has electrode areas formed by ion implantation such that the interface level is formed near the surface thereof; an insulating diamond layer formed on a portion of the semiconducting diamond layer; a source electrode made of a degenerate diamond film provided in one of the electrode areas of the semiconducting diamond layer, to form an ohmic contact between the same and the semiconducting diamond layer; a drain electrode made of a degenerate diamond film provided in the other of the electrode areas of the semiconducting diamond layer, to form an ohmic contact between the same and the semiconducting diamond layer; and a gate electrode made of a degenerate diamond film formed on the insulating diamond layer, to form a Schottky junction between the same and the semiconducting diamond layer through the diamond insulating layer.

Abstract: A semiconductor light emitting element with a high light-emitting efficiency, which is constituted in such a way that, of the composition of its GaN and AlN epitaxial layer, part of N is substituted by P, thus ensuring good lattice-matching with the substrate crystal, ZnO.

Abstract: A metal oxide semiconductor field effect transistor with heterostructure has a silicon substrate. Heavily-doped source and drain layers which are different in conductivity type from the substrate are spaced apart from each other in the surface portion of the substrate. A gate electrode of polycrystalline silicon is disposed above the substrate, and is electrically insulated from the substrate by a gate insulation layer made of thermal silicon oxide thin film. A silicon germanium layer is laterally provided in a preselected substrate surface section positioned between the source and drain layers. This layer partially overlaps the source and drain layers at both of its end portions, and is thus electrically in contact with these layers. The silicon germanium layer acts as a channel of the transistor.

Abstract: An IC card comprises a card board having first and second major surfaces and a semiconductor module having an electrode terminal face. The semiconductor module is mounted in the card board, so that the electrode terminal face is exposed onto the first major surface of the card board. The card board comprises a board frame and a resin which is molded inside the board frame. Part of the semiconductor module surface which is opposite to the electrode terminal face, is covered with the resin.

Abstract: Technology for using a wiring of a superconductive material in semiconductor integrated circuit device. An isolation layer and/or a barrier layer are provided for preventing diffusion of harmful composition of the superconductive material for the semiconductor device. Control of a circuit can be made utilizing the characteristics of a superconductive material. Also, the characteristics of a superconductive material may be controlled. A method of forming a layer of superconductive material, well compatible with the widely used process of manufacturing integrated circuit devices, is also disclosed.

Abstract: According to the present invention, the hetero junction bipolar transistor (HBT) is provided which includes an emitter layer consisting of a first semiconductor of a first conductive type and being in mesa form; a base layer being in contact with the emitter layer and consisting of a second semiconductor of a second conductive type having a narrower band gap than the first semiconductor; and a collector layer being in contact with the base layer and consisting of a third semiconductor of a first conductive type having a broader band gap than the second semiconductor. In this HBT, a monolayer sulfur film is formed so as to cover the exposed periphery of the heterointerface between the emitter layer and the base layer.

Abstract: A device for generating pulses of radio frequency energy in response to pulses of laser light in which a circular wafer of GaAs has metallized annular layers ohmically bonded to the wafer by epitaxial GaAs layers, and an epitaxial layer of AlGaAs in the center of one of the annular epitaxial layers through which laser light is to be directed, there being a plurality of apertures in the metallized layer in contact with the AlGaAs epitaxial layer. In addition, an AlGaAs epitaxial layer may be formed opposite the first AlGaAs layer and an optical fiber is brought into contact with it so that laser light can be introduced at both sides of the wafer.

Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

Abstract: A tunnel junction type superconducting device includes a pair of superconductor electrodes formed of compound oxide superconductor material, and a metal layer of a high electric conductivity formed between the pair of superconductor electrodes so as to maintain the pair of superconductor electrodes separate from each other. The pair of superconductor electrodes is separated from each other by a distance within a range of 3 nm to 70 nm by action of the metal layer.

Abstract: A method including covering the area to be laser trimmed with a first insulative layer having a thickness sufficiently thin that a layer can trim the area through the first insulative layer. An etch stop is formed on the first insulative layer over the area to be trimmed and covered with a second insulative layer. A portion of the second insulative layer is etched to expose the etch stop and a portion of the etch stop is then removed to expose a portion of the first insulative layer and laser trimming is conducted through the exposed first insulative layer. The etch stop is part of a first level of interconnects made of the same material and simultaneously with the etch stop. The area to be trimmed is part of a second level of contacts that interconnect another second material.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: A novel light emitting semiconductor device is disclosed. The device utilizes real space transfer (RST) of carriers, and comprises regions of opposite conductivity type separated by a barrier layer. The first region (termed the "emitter") comprises at least two contacts. Application of appropriate bias between the two contacts and between the emitter and the second region results in injection of hot carriers into the second region, resulting in luminescence in the second region. The invention can be embodied in coherent as well as incoherent light sources. A preferred embodiment is a vertical cavity surface emitting laser. The device can serve as a novel logic element that has electrical inputs and an optical output, and provides a non-trivial logic function.