Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

Abstract: A non-volatile memory device in which gate electrodes are formed on an upper surface and a lower surface of the channel via insulating layers, respectively, one of them is used as a read electrode and the other is used as a write electrode, whereby, at a read operation, the reading is carried out with a reduced influence upon stored charges stored at the time of writing. Particularly, it has a structure in which a source and drain region of the non-volatile semiconductor memory device is formed in the semiconductor layer formed on the insulating layer and, at the same time, one of the read electrode and write electrode is buried in the insulating layer.

Abstract: A bottom lead semiconductor chip stack package which includes a first body and a second body. The first body includes a pair of lead frames, each lead frame having a first lead portion and a second lead portion. A protrusion enclosed in a solder extends from the first lead portion. The first body also includes a semiconductor chip containing chip pads disposed on the surface thereof, the chip pads being connected to the solder enclosed protrusions. The second body has substantially the same structural configurations as the first body and is reversely stacked relative to the first body such that the semiconductor chips are disposed in opposing relationship relative to each other. An adhesive attaches the lead frames of the first body to the corresponding lead frames of the second body.

Abstract: A resistive structure formed on an integrated circuit substrate is disclosed. The structure includes a plurality of resistive elements serially connected. Each resistive element comprises a forward biased semiconductor junction and a reverse biased semiconductor junction. The resistive value of each resistive element can be varied with a preferred range being from about 500 megohms to about 5 gigaohms. In fabrication, the multiple resistive elements are electrically and physically simultaneously formed and are connected in series to obtain higher resistive values. The disclosed resistive structure allows very high resistances to be obtained using very little planar surface area.

Abstract: A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive.

Abstract: A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

Abstract: A monolithic type active matrix semiconductor device comprises a substrate having an insulating surface, a first plurality of thin film transistors formed on the substrate, each having a first channel region comprising an amorphous silicon semiconductor film, and a second plurality of thin film transistors, each having a second channel region comprising a crystalline semiconductor film. The crystalline semiconductor film of the second plurality of thin film transistors has a substantially single crystalline structure (mono-domain structure) and is doped with a recombination center neutralizer at a concentration of 1.times.10.sup.16 to 1.times.10.sup.20 atoms/cm.sup.3. The crystalline semiconductor film of the second plurality of thin film transistors contains a catalyst element which is capable of promoting crystallization of silicon.

Abstract: Burst pressure P of an insulating layer positioned immediately on a fuse layer is defined by using planar width W of fuse layer and thickness t of insulating layer. The value of the planar width W of fuse layer and the value of the thickness t of insulating layer are set such that the value of burst pressure P is at most about 1000 kg/cm.sup.2. The value of the thickness t and the value of the planar width W are set such that the value t/W is at least 0.45 and at most 0.91. Consequently, stable fuse blowing becomes possible while reducing manufacturing cost.

Abstract: In a circuit configuration comprising an n-channel thin-film transistor and a p-channel thin-film transistor integrally produced on a single substrate, a lightly-doped drain (LDD) region is formed selectively in the n-channel thin-film transistor, and damages to semiconductor layers caused when implanting impurity ions are balanced between the n- and p-channel thin-film transistors. This configuration achieves a balance between the n- and p-channel thin-film transistors and thereby provides high characteristics CMOS circuit.

Abstract: A electronic apparatus and a process for its manufacture are disclosed. The apparatus includes a planar card for accommodating an electronics module package having protruding solder columns and solder joints to mechanically mount and electrically connect the solder columns of the module to the planar card. The planar card includes a first side and a second side, a plurality of wiring lines forming a wiring pattern, and a plurality of vias extending at least partially through the card. Each of the vias includes at least one recessed area extending from one or both sides of the card. The recessed areas extending to a depth within the planar card sufficient to wick the solder joints, and the each of the recessed areas are shaped to provide surface tension to mechanically retain the solder joints.

Abstract: The invention relates to a polysilicon resistor made by forming a film of polysilicon doped with an impurity on a dielectric film on a semiconductor substrate and patterning the polysilicon film. An object of the invention is to provide a polysilicon resistor which has a low resistance value and occupies a small area. A slot is formed in the dielectric film and is filled with the polysilicon film. The dielectric film and the patterned polysilicon film are overlaid with a second dielectric film, and a pair of contact windows are opened in the second dielectric film such that each contact window is partly over an end section of the slot. A plurality of parallel slots can be formed in the first dielectric film to further lower the resistance value or to further reduce the area of the patterned polysilicon film. As an alternative, at least one slot is formed in the substrate and is filled with a polysilicon film after depositing a dielectric film on the substrate surface including the surfaces in the slot(s).

Abstract: The flash EEPROM cell of split-gate type according to the present invention can prevent the degradation of the tunnel oxide film of the cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap region between the junction region and the gate electrode when programming and erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film.

Abstract: A semiconductor memory device wherein source lines of a memory cell array constituted by a plurality of memory cells arranged in the form of a matrix at intersecting points of word lines and bit lines are arranged in a row direction or a column direction and the source lines of the nonselected rows or the nonselected columns are inversely biased with respect to the semiconductor substrate, thereby to prevent erroneous reading by the leakage current at the time of reading data and further reduce the write current at the time of writing. Further, the read operation is kept from deteriorating by reducing the amplitude of the source line at the time of reading by setting the inverse bias voltage at a minimum constant voltage smaller than the power source voltage.

Abstract: A method for fabricating a semiconductor integrated circuit includes the steps of providing a conductor film on a substrate, providing an insulator film on the conductor film to form a layered structure, removing the insulator film selectively from a first part thereof corresponding to a conductor pattern to be formed, while remaining the insulator film on a second part thereof corresponding also to a conductor pattern to be formed, patterning the layered structure to form a conductor pattern defined by side walls, providing a side wall insulation to each of the side walls of the conductor pattern, providing a first local interconnect pattern on the first part of the conductor pattern such that the first local interconnect pattern establishes an electrical connection with the conductor pattern at the first part, and providing a second local interconnect pattern on the second part of the conductor pattern such that the second local interconnect pattern bridges across the conductor pattern at the second part, w

Abstract: An ESD protection device is provided which reduces the layout area required, utilizing multiple-node configurations and multiple node electrical couplings.

Abstract: An interlayer insulating layer is formed to cover a fuse layer. A concave portion is provided on the surface of interlayer insulating layer located directly above fuse layer. A nitride layer as a passivation layer extends on the sidewalls of concave portion. In this way, a semiconductor device is obtained, the device having an improved moisture resistance, and in which a fuse can be easily blown by laser and a design rule of the region adjacent to the fuse can be improved.

Abstract: A highly integrated flash memory device having a stable cell is provided.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

Abstract: A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating firm is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.