Patents Examined by Vaness Perez-Ramos
  • Patent number: 6465351
    Abstract: A method for fabricating a capacitor is provided that can reduce the number of CMP processes. It avoids the use of a CMP process on an uneven interlayer insulating layer on which a storage node is to be formed, by employing a process of forming a sacrificial oxide layer on the uneven interlayer insulating layer, forming a CMP stopper layer, forming another oxide layer, etching the deposited layers until a top surface of uneven interlayer insulating layer is exposed to form a trench therein for a storage node, depositing a conductive material in the trench and on the another oxide, and performing a CMP process until a top surface of the CMP stopper layer is exposed to electrically separate each storage node from another. The remainder of the oxide layer on the CMP stopper layer is then removed and then the CMP stopper layer is removed.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: October 15, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-Kwon Jeong