Abstract: Using plasma enhanced chemical vapor deposition, various layers can be deposited on semiconductor substrates at low temperatures in the same reactor. When a titanium nitride film is required, a titanium film can be initially deposited using a plasma enhanced chemical vapor deposition wherein the plasma is created within 25 mm of the substrate surface, supplying a uniform plasma across the surface. The deposited film can be subjected to an ammonia anneal, again using a plasma of ammonia created within 25 mm of the substrate surface, followed by the plasma enhanced chemical vapor deposition of titanium nitride by creating a plasma of titanium tetrachloride and ammonia within 25 mm of the substrate surface. This permits deposition film and annealing at relatively low temperatures--less than 800.degree. C.

Abstract: A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e.g., by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts. The purge process is benign in that it only uses equipment and procedures of the type used during product wafer processing.

Abstract: A semiconductor substrate is supported on a lower electrode provided within a chamber. The semiconductor substrate is heated up to about 600.degree. to 700.degree. by radiation heat from a halogen lamp. While the pressure within the chamber is reduced to about 0.1 to 1 Torr, the lower electrode is used as a positive electrode, and an upper electrode is used as a negative electrode. In this state, a DC voltage of 20 V is applied from a DC power supply. Then, a material gas is introduced into the chamber via an introducing hole, and a polysilicon film is grown on an oxide film on the semiconductor substrate. Electricity in the oxide film increases an initial growth rate of the polysilicon film and prevents formation of pinholes in the polysilicon film.

Abstract: An apparatus for breaking a wafer into individual devices, and a method of using the same. An anvil 100 is pressed against a flexible membrane 304 on which a wafer 300 is attached. A vacuum is applied to the anvil 100 which allows the flexible membrane 304 and the wafer 300 to be pressed against the face of the anvil 100. As the flexible membrane 304 is deformed against the anvil 100, the wafer 300 breaks into individual devices 302. Dicing debris that is created when the wafer 300 is broken falls into a base fixture 408 so that the debris does not contact and damage the devices 302.

Abstract: To provide a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus in which both a dependency on base material and a film characteristic are satisfied in film forming steps of the semiconductor manufacturing. There are provided a first film forming part 4 and a second film forming part 5 along a transporting direction A in the transporting system 1 for the semiconductor substrate 2, the first film forming part 4 is provided with a post-mixed type gas supplying means 7 for supplying a plurality of kinds of reaction gases onto a semiconductor substrate while the gases are being separated from each other through an inert gas, and the second film forming part 5 is provided with a premixed type gas supplying means 8 for supplying the mixture gas onto the semiconductor substrate while a plurality of kinds of reaction gases are mixed in advance.

Abstract: The present invention provides a method of manufacturing a void free, reduced stress aluminum layer and an overlying silicon nitride layer on a substrate, comprising: forming a gate oxide layer 12 over said substrate, forming a polysilicon layer 14 over said gate oxide layer 12; forming a polyoxide layer 16 over said polysilicon layer 14; forming a first insulating layer 18 composed of silicon nitride over said polyoxide layer 16; forming an aluminum alloy layer 20 over said first insulating layer; forming a silicon nitride layer 24 over said aluminum alloy layer 20 by ramping said substrate from room temperature up to between about 345.degree. and 355.degree. C., at a pressure between about 2200 and 2500 m torr, in a N.sub.2 ambient, for time of between about 3 and 8 minutes; and ramping the temperature down to between 315.degree. and 325.degree. C. and depositing silicon nitride over said aluminum layer at a temperature of between about 315.degree. and 325.degree. C.

Abstract: A method of forming a stable semiconductor device on an at least partially completed semiconductor device including a supporting semiconductor structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer structure. A relatively thin layer of Ga.sub.2 O.sub.3 is deposited on the surface by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide, such as MgO or Gd.sub.2 O.sub.3. A second layer of material with low bulk trap density relative to the Ga.sub.2 O.sub.3 is deposited on the layer of Ga.sub.2 O.sub.3 to complete the dielectric layer structure.

Abstract: A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Abstract: The invention relates to a method and to apparatus for processing a specimen, particularly an integrated circuit, in which an area of the specimen to be processed is scanned with a corpuscular beam and at least one gas is supplied above the area to be processed so that with the aid of the corpuscular beam a chemical reaction takes place on the area to be processed. The processing speed can be markedly increased by the use of a magnetic field in the region of the probe.

Abstract: A method for producing a thin semiconductor film according to the present invention includes the steps of: placing a group-IV compound or a derivative thereof in a plasma state; decomposing the group-IV compound or the derivative thereof into active species; and depositing the active species on a substrate, wherein energy for generating plasma is intermittently supplied at a supply time interval which is equal to or less than a reciprocal of {(secondary reaction rate constant of a source gas reacting with active species other than long-life active species within the plasma).times.(number of source gas molecules)}.

Abstract: A method of eliminating or substantially eliminating voids formed in the bottom of high aspect ratio holes following the physical vapor deposition of a material over the surface of a substrate. The method includes placing the substrate in an ultrasonic processing chamber filled with a fluid and having an ultrasonic source. The ultrasonic source is used to generate ultrasonic waves at a frequency no higher than is sufficient to cause a flow of the material adjacent the voids into these voids, without significantly affecting the deposited material elsewhere on the substrate.

Abstract: The present invention concerns a method for making an identification mark on a silicon surface. In a preferred embodiment, the identification mark formed on the silicon surface does not substantially score the silicon. A silicon or silicon dioxide surface coated with an insulating layer is marked by laser scribing, leaving an exposed area on the silicon or the silicon dioxide. The exposed area on the silicon wafer is preferably not marked by the laser scribing. The exposed silicon surface is then oxidized by dry or wet oxidizing. The silicon oxide can be subsequently removed to leave an etched mark. The method reduces or eliminates the formation of stresses and silicon slag at the etched mark that can cause defects and reduce yield.

Abstract: An apparatus for releasably clamping a substrate to a support platform, or other support means, at a face of the substrate is described. In one embodiment, a retractable clamp holds a substrate near its edges on a support platform when the clamp is in its fully extended position. One or more leaf springs are mounted to the clamp and apply force to the substrate at respective points in the event the substrate adheres to the clamp, thereby releasing the substrate from the clamp. In a preferred embodiment of the present invention, one or more activators are positioned in cooperative relationship to the leaf springs to cause the leaf springs to retract into recesses in the clamp when the clamp is extended against the substrate. In their retracted position, the leaf springs do not contact the substrate so as to minimize the generation of particle contamination and the chance of the release leaf springs themselves adhering to the substrate.