Abstract: A method and apparatus for releasably attaching a planarizing medium, such as a polishing pad, to the platen of a chemical-mechanical planarization machine. In one embodiment, the apparatus can include several apertures in the upper surface of the platen that are coupled to a vacuum source. When a vacuum is drawn through the apertures in the platen, the polishing pad is drawn tightly against the platen and may therefore be less likely to wrinkle when a semiconductor substrate is engaged with the polishing pad during planarization. When the vacuum is released, the polishing pad can be easily separated from the platen. The apparatus can further include a liquid trap to separate liquid from the fluid drawn by the vacuum source through the apertures, and can also include a releasable stop to prevent the polishing pad from separating from the platen should the vacuum source be deactivated while the platen is in motion.

Abstract: A process for forming a bump via to interconnect upper and lower circuits wherein a layer of metal is etched down, leaving a bump via and a lower portion of the layer. A lower circuit pattern is then formed in the lower portion, following which the pattern and bump via are covered with an insulating layer. Smoothing then results in the top surface of the bump via being exposed such that an upper circuit can then be formed on the insulating layer and in connection with said bump via.

Abstract: The present invention provides a method of manufacturing an integrated circuit using a cleaning brush and a cleaning brush conditioning apparatus. In one embodiment, the cleaning brush conditioning apparatus comprises a conditioning bar and a load cell coupled to the conditioning bar. The load cell is configured to force the conditioning bar against the cleaning brush.

Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.

Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

Abstract: Methods are disclosed for gas-cluster ion-beam deposition of thin films on silicon wafers rendered free of native oxides by termination of the surface bonds and subsequent reactive deposition. Hydrogen termination of the surface of silicon renders it inert to reoxidation from oxygen-containing environmental gasses, even those found as residue in vacuum systems, such as those used to deposit films. Nitrogen termination improves the interface with overlying metal-oxide thin films. The film is formed in intimate contact with the silicon crystal surface forming a nearly ideal interface.

Abstract: A microelectronic component is made by providing a starting structure having a dielectric layer and leads on a surface of the dielectric layer. Ends of the leads are connected to contacts on a microelectronic element, such as the contacts on a semiconductor chip or wafer. The dielectric layer is then etched to partially detach the leads from the dielectric layer, leaving at least one end of each lead permanently connected to the dielectric layer. The remainder of the lead may be fully or partially detached from the dielectric layer. If the remainder of the lead is only partially detached, the connecting elements that connects the leads to the polymeric layer can be broken or peeled away from the leads during the step of moving the microelectronic element and dielectric layer away from one another.

Abstract: An etch process utilizing Cl2/He chemistry for use in a silicon integrated circuit manufacturing process. The etch is a highly nitride selective, anisotropic etch. The process according to an aspect of the invention comprises the steps of etching through a top silicon dioxide layer of an ONO layer with a C12/He plasma etch at a first power, and subsequently etching the underlying nitride layer at a substantially lower second power.

Abstract: In a semiconductor device fabricating process, a copper-based metal film is formed on an insulating layer, and an insulating film is formed on the copper-based metal film. A patterned resist film is formed on the insulating film, and the insulating film is dry-etched using the patterned resist film as a mask to form a hole penetrating through the insulating film. Thereafter, a plasma treatment using an non-oxidizing gas is carried out, and furthermore, a wet treatment using a resist remover liquid is carried out, for removing the resist film and a resist surface hardened layer which was generated in the dry-etching.

Abstract: A method for fabricating a semiconductor device including a semiconductor layer structure, a source electrode and, a drain electrode formed on the semiconductor layer structure, and a source interconnection connected to the source electrode is provided. The method includes the steps of: (a) forming the semiconductor layer structure on a substrate; (b) forming a metal layer structure so as to cover the semiconductor layer structure; (c) forming a resist layer having a predetermined pattern on the metal layer structure: (d) performing a first etching process for the metal layer structure using the resist layer as a mask so as to form the source electrode, the drain electrode and the source interconnection; and (e) performing a second etching process for the semiconductor layer structure using the resist layer as a mask so as to form a transistor gap portion between the source electrode and the drain electrode.

Abstract: A CMP slurry includes a first emulsion having a continuous aqueous phase and a second emulsion. The first emulsion includes abrasive particles, and the second emulsion captures metal particles polished from the semiconductor wafer. Thus, metal particles can be removed from the slurry during CMP to avoid damaging and/or contaminating the semiconductor wafer.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: A method for determining the AB etch endpoint during an silicon trench isolation fabrication process requires the introduction into the STI design a sufficient quantity of “dummy” diffusion structures that provide a strong endpoint signal during normal STI fabrication and, that which endpoint signal may be controlled by adjustment of the planarization shapes associated with the dummy diffusion structures.

Abstract: A polishing composition comprising the following components: (a) an abrasive, (b) &agr;-alanine, (c) hydrogen peroxide, and (d) water.

Abstract: The copper-based metal polishing composition causes Cu or Cu alloy not to be dissolved at all in immersing Cu or Cu alloy therein, and makes it possible to polish Cu or Cu alloy at a high rate in polishing treatment. Such a copper-based metal polishing composition comprises a water-soluble first organic acid capable of reaction with copper to produce a copper complex compound which is substantially insoluble in water and has a mechanical strength lower than that of copper, at least one second organic acid selected from an organic acid having a single carboxyl group and a single hydroxyl group and oxalic acid, an abrasive grain, an oxidizing agent, and water.

Abstract: A method of processing a workpiece in a plasma reactor includes establishing a torroidal path for a plasma current to flow that passes near and transverse to the surface of said workpiece, maintaining a plasma current in the torroidal path by applying RF power to a portion of the torroidal path away from the surface of the workpiece, and increasing the ion density of the plasma current in the vicinity of the workpiece by constricting the area of a portion of the torroidal path overlying the workpiece.

Abstract: A method for plasma etching, comprising etching a structure with a plasma prepared from a gas mixture comprising: (i) an etching gas, and (ii) a strained cyclic (hydro)fluorocarbon gas, has a high etch selectivity of oxide versus nitride, and is particularly useful in a SAC etch process.

Abstract: A method is provided for forming separated spacer structures in a mixed-mode integrated circuit, which can be used to form spacer structures with different widths for the various kinds of devices in the mixed-mode integrated circuit. The method is for use on a semiconductor substrate which is formed with at least a first gate for a first kind of device of the mixed-mode integrated circuit and a second gate for a second kind of device of the integrated circuit, with the second gate being larger in width than the first gate such that the first gate is formed with a first spacer structure on the sidewalls thereof to a first desired width while the second gate is formed with a second spacer structure on the sidewalls thereof to a second desired width larger than the first desired width.

Abstract: There is disclosed a method of processing a work comprising polishing a work holding surface 4a of a work holding plate 4 by contacting and rubbing a work holding surface 4a of a work holding plate 4 with a polishing pad 2 attached on a polishing turn table 1 with providing polishing agent 5 thereto, holding a wafer W on said work holding surface 4a by vacuum-holding, and contacting and rubbing the wafer W with said polishing pad 2 to polish the work with providing polishing agent 5 wherein temperature of the polishing agent 5 or the polishing turn table 1 is controlled by temperature controller 7,9 so that a temperature of said work holding surface 4a when polishing said work holding plate 4 and a temperature of said work holding surface 4a when polishing the wafer w are controlled to be the same.

Abstract: A system and method for reducing contamination in a semiconductor device formed on a substrate is disclosed. The method and system include providing a barrier metal layer on the substrate. A first portion of the barrier metal layer is thinner than a second portion of the barrier metal layer. The method and system further include removing the first portion of the barrier metal layer.