Abstract: The present invention provides a method for cleaning a contaminated chamber used in the manufacture of semiconductor devices. In one embodiment, the method comprises the steps of injecting, under pressure, a gas mixture of a fluorine-containing gas and an inert gas into the contaminated chamber, radiating the contaminated chamber with a radio frequency during the step of injecting, and removing volatile by-products or solid particulates from the contaminated chamber by performing pump-purge cycles within the contaminated chamber.

Abstract: A method of fabricating a node contact opening includes formation of a dielectric layer on a substrate. An opening is formed with C4F8/Ar/CH2F2 as an etchant. A portion of the dielectric layer under the opening is etched with CHF3/CO as an etchant until the substrate is exposed. A node contact opening is formed.

Abstract: A method for reducing polymer deposition on vertical surfaces of metal lines etched from a metallization layer disposed above a substrate. The method includes forming a hard mask layer above the metallization layer and providing a photoresist mask above the hard mask layer. The method further includes employing the photoresist mask to form a hard mask from the hard mask layer. The hard mask has patterns therein configured to form the metal lines in a subsequent plasma-enhanced metallization etch. There is also included removing the photoresist mask. Additionally, there is included performing the plasma-enhanced metallization etch employing the hard mask and an etchant source gas that includes Cl2 and at least one passivation-forming chemical, wherein the plasma-enhanced metallization etch is performed without employing photoresist to reduce the polymer deposition during the plasma-enhanced metallization etch.

Abstract: A cluster tool method using plasma immersion ion implantation chamber. In some embodiments, the cluster tool method also includes a controlled cleaving process chamber, as well as others.

Abstract: A method and apparatus for gold etching in semiconductor circuit manufacturing. An environmentally safe etching solution is used in an electroplating device to etch gold from a semiconductor substrate. The etching solution is free of iodine and cyanide based compounds and preferably includes thiourea.

Abstract: A method of fabricating a self-aligned contact window includes forming an undoped dielectric layer on a substrate having a least gate structure. The dopants are implanted into a pre-determined region of the undoped dielectric layer and the dielectric layer with the dopants is then removed. A self-aligned contact is therefore completed.

Abstract: An integrated circuit fabrication process in which residual fluorine contamination on metal surfaces after ashing is removed by exposure to an NH.sub.3 /O.sub.2 plasma.

Abstract: The invention provides a process and apparatus for improving the accuracy of plasma etching processes such as trench and recess etch processes. In such processes, a trench or recess is etched into a layer of material which does not have a stop layer at the desired depth of the etched openings. Instead, the etching process is carried out for a set time period calculated to achieve a desired etch depth on the basis of measured or estimated etching rates. For example, the duration of etching to achieve a target depth may be based on statistical analysis or real-time measurements of etch depths by interferometry. However, use of estimated etching rates or interferometry to control when etching should be terminated to achieve a desired etch depth can result in defective structures due to etched openings which are too deep or too shallow.

Abstract: A method of producing etched structures in substrates by anisotropic plasma etching, wherein an essentially isotropic etching operation and side wall passivation are performed separately and in alternation, with the substrate being a polymer, a metal or a multicomponent system, and portions of the side wall passivation layer applied during passivation of the side wall are transferred to the exposed side surfaces of the side wall during the subsequent etching operations, so the entire method is anisotropic as a whole.

Abstract: A photo-resist mask is removed from an inter-level insulating structure by using plasma produced from N.sub.x H.sub.y gas, and the plasma does not make an organic insulating layer forming part of the inter-level insulating structure hygroscopic, because SiCH.sub.3 bond is never replaced with Si--OH bond during the removal of the photo-resist mask.

Abstract: Methods of forming substantially defect-free silicon structures at the submicron level by enhancing microscopic etchant concentration uniformity and reducing hydrogen bubble adhesion. Etchant mixtures are subjected to the application of ultrasonic waves. The ultrasonic waves promote cavitation that mixes the etchant mixture on a microscopic level, and also assists in promoting bubble detachment. Wetting agents are added to the etchant mixture to enhance the hydrophilicity of the silicon surfaces and thereby reduce bubble adhesion. Apparatus to carry out the method of forming silicon structures are also disclosed.

Abstract: A method for etching through a low capacitance dielectric layer in a plasma processing chamber. The low capacitance dielectric layer is disposed below a hard mask layer on a substrate. The method includes flowing an etch chemistry that includes N.sub.2 and H.sub.2 into the plasma processing chamber. There is included creating a plasma out of the etch chemistry. The method also includes etching, using the plasma, through the low capacitance dielectric layer through openings in the hard mask layer in the plasma processing chamber.

Abstract: The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.

Abstract: The problem of key-hole formation during the filling of small diameter via holes has been overcome by means of soft sputtering in argon after the barrier layer is in place. This sputtering step may be used twice--once to widen the mouth of a newly formed via hole, and a second time after the barrier layer is in place, thereby widening the mouth further (as well as removing oxide from the surface of the barrier layer). In an alternate optional embodiment, widening of the via hole mouth may be limited to a single sputtering step after the barrier layer has been laid down. In either case, this is followed by filling of the via hole which occurs without any key-hole formation.

Abstract: A process for forming a semiconductor device using a conductive etch stop. The process includes the steps of fabricating a wafer structure up to a first level oxide deposition. A conductive etch stop is deposited over the first level oxide deposition, and selected portions of the conductive etch stop are removed. An inter-level oxide layer is deposited on the conductive etch stop, and selected portions of the inter-level oxide deposition are etched up to the conductive etch stop. The conductive etch stop may be either removed from the semiconductor or left as a conductor.

Abstract: Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). The first disposable gate structure (26) may comprise a replaceable material. A second disposable gate structure (28) of the second complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A replacement layer (70) may be formed over the first disposable gate structure (26). The replacement layer (70) may comprise a replacement material. At least a portion of the replaceable material of the first disposable gate structure (26) may be substitutionally replaced with the replacement material of the replacement layer (70) to form a first gate structure (80).

Abstract: A method of patterning a layer on sidewalls of a trench in a substrate for integrated circuits includes the steps of forming an insulator layer on sidewalls of a trench in a substrate with a horizontal top surface above the sidewalls, recessing a masking material such as an organic photoresist in the trench below the top surface of the substrate such that a portion of the insulator layer on the sidewalls of the substrate is exposed, and etching the insulator layer with a gaseous hydrogen flouride-ammonia mixture. The masking material and the substrate are composed of a different material than the insulator layer.

Abstract: A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

Abstract: A method for producing a semiconductor device capable of stably removing a sidewall mask layer without removal of an etching stopper film, wherein a conductive layer 30 and a first diffusion layer 11 are formed in a semiconductor substrate 10, an etching stopper film 21 is formed covering the conductive layer 30, a sidewall mask layer 31b containing silicon is formed at an upper layer of the etching stopper film 21 facing a sidewall surface of the conductive layer 30, and a second diffusion layer 12 is formed. Here, a conductive impurity is introduced into at least the sidewall mask layer 31b at either of the time of formation of the sidewall mask layer 31b or the time of formation of the second diffusion layer 12, and heat treatment for activating the conductive impurity in the sidewall mask layer 31b is applied.

Abstract: In a method of manufacturing an optical semiconductor device having a semiconductor substrate, an optical waveguide formed by a semiconductor layer is formed on the semiconductor substrate by the use of the selective metal-organic vapor phase epitaxy including source materials. The source materials are intermittently supplied in the selective metal-organic vapor phase epitaxy.