Abstract: The present invention relates to a biochip for capacitive stimulation and/or detection of biological tissue. The biochip includes a support structure, at least one stimulation and/or sensor device, which is arranged in or on the support structure, and at least one dielectric layer, one layer surface of which is arranged on the stimulation and/or sensor device and the opposite layer surface forms a stimulation and/or sensor surface for the capacitive stimulation and/or detection of biological tissue. The dielectric layer includes (Tix, Zr1-x)O2, with 0.99?x?0.5, or a TiO2 and ZrO2 layer arrangement.

Abstract: A semiconductor photocathode comprises a p+-type semiconductor substrate of GaSb, and a p?-type light absorbing layer of InAsSb. A p+-type hole blocking layer is formed between the substrate and the light absorbing layer having wider energy band gap than that of the light absorbing layer, the blocking layer being made of AlGaSb.

Abstract: The present invention is related to an Electrostatic Discharge protection device. This may be a semiconductor device such as a CMOS transistor, having a snap-back IV characteristic, in order to withstand ESD pulses. The device of the invention comprises an additional doped region, which influences the internal resistance of the substrate whereupon the device is built. This has a positive effect on the snap-back characteristic, putting the snap back trigger voltage and current at a lower value, compared to prior art devices.

Abstract: In one embodiment, an interconnect line on one level of an integrated circuit is electrically coupled to another interconnect line on another level. The two layers of interconnects may be coupled together using a via. To reduce capacitance between the interconnect lines, an air core is formed between them. The air core may be formed by using a chemistry that includes a noble gas fluoride to etch a sacrificial layer between the interconnect layers.

Abstract: Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate 10, a floating gate 22 disposed above the silicon substrate 10 through a first dielectric layer 20, a second dielectric layer 26 that contacts at least a part of the floating gate 22, a control gate 28 formed over the second dielectric layer 26, and a source region 14 and a drain region 16 formed in the silicon substrate 10. A wiring layer 40 is provided above the floating gate 22, and the entirety of the floating gate 22 is overlapped by the wiring layer 40 as viewed in a plan view.

Abstract: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the gap between pixels from light, and a thin film transistor is arranged so as to partially overlap a gate wiring (166) for shielding a channel region of the thin film transistor from light, thereby realizing a high pixel aperture ratio.

Abstract: A lead frame for use in solid state relays has a teardrop shaped frame. The frame has a small rounded portion connected to a large rounded portion. A power semiconductor is mounted in the large rounded portion. The teardrop shape eliminates sharp corners found in rectangular frames and allows heat to dissipate radially in all directions. More metal in close proximity to the power semiconductor, maintaining a lower aspect ratio of length to width, allows the semiconductor to run cooler at any given load. Several vent holes are located in the small rounded portion, which act as exhaust ports for the fumes generated in the heating stage of the solder re-flow, increasing solder coverage and improving reliability. The life of solder junctions utilizing the teardrop shaped lead frame which are subjected to temperature cycling while under load is increased, thus extending the life of the solid state relay.

Abstract: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600° C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.

Abstract: Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.

Abstract: The traditional nitride-only charge storage layer of a SONOS device is replaced by a multifilm charge storage layer comprising more than one dielectric material. Examples of such a multifilm charge storage layer are alternating layers of silicon nitride and silicon dioxide, or alternating layers of silicon nitride and aluminum oxide. The use of more than one material introduces additional barriers to migration of charge carriers within the charge storage layer, and improves both endurance and retention of a SONOS-type memory cell comprising such a charge storage layer.

Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

Abstract: A rectification chip terminal structure for soldering a rectification chip encased in a glass passivated pallet (GPP) on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a conductive element which has a buffer portion and a base seat to prevent the GPP from fracturing when the packaging material is heated and expanded or prevent the conductive element from bending and deforming under external forces, and has a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can prevent the GPP from fracturing when the packaging material is heated and expanded and be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Abstract: A semiconductor device allows a second seal portion 8 made of a conductive resin to function as an electromagnetic wave shield for a photodetector 3 and a control IC chip 5 sealed with a first seal portion 7 made of a light-transmitting resin, when a third lead 1c for grounding of a lead frame 1 is connected to a ground terminal on a board. Conductive portions 21, 22 of the second seal portion 8 fill through holes 16, 17 provided for projecting portions 10, 11 of the lead frame 1 so as to be in close contact with peripheral surfaces 16A, 17A of the through holes 16, 17. The through holes 16, 17 have peripheral surfaces 16A, 17A of a rectangular-columnar shape. The semiconductor device is capable of obtaining a sufficient electromagnetic shielding effect, while it is small and low-cost, having a high degree of mounting freedom on a board.

Abstract: A semiconductor device includes a silicon layer on an insulating layer. The silicon layer has a first area and a second area. An FD-MOSFET is formed in the first area and a PD-MOSFET is formed in the second area. The semiconductor device satisfies the following formulas: the thickness of the silicon layer is 28 nm to 42 nm, the impurity concentration Df cm?3 of the first area is Df?9.29*1015*(62.46?ts) and Df?2.64*1015*(128.35?ts), and the impurity concentration Dp of the second area is Dp?9.29*1015*(62.46?ts) and Dp?2.64*1015*(129.78?ts).

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y?0) and a peripheral region including an amorphous or polycrystalline Si1-x-yGexCy layer which surrounds the island region on a monocrystalline Si layer on an insulating film, a step of subjecting the respective Si1-x-yGexCy layers to heat treatment, and after the heat treatment and the removal of a surface oxide film, a step of forming a monocrystalline Si1-z-wGezCw layer (1>z?0, 1>w?0) which becomes an element formation region on the island region.

Abstract: An electrostatic discharge (ESD) protection circuit is provided for protecting transistors of an integrated circuit (IC) from ESD. The ESD protection circuit includes n transistors with n gates and less than n drains where n is an integer greater than 1. At least m resistors have first ends that communicate with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC, and second ends that connect to corresponding drain terminals of said drains where m is an integer greater than or equal to n/2.

Abstract: A semiconductor device having at least two layers formed on a semiconductor substrate includes a first dielectric layer formed on the semiconductor substrate; a first interconnection layer which is formed on the first dielectric layer and has a first interconnection pattern and a dummy pattern formed around the first interconnection pattern; a second dielectric layer formed on the first interconnection layer; and a second interconnection layer which is formed on the second dielectric layer and has a second interconnection pattern. The dummy pattern is placed in the vicinity of only an area where the first and second interconnection patterns are superposed on each other.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads.