Abstract: A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

Abstract: An apparatus includes a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels for representing physical locations of the circuit components within the apparatus.

Abstract: A memory device includes a bit line group having a first bit line and a second bit line. The bit line group includes a first segment, a second segment, and a twist segment conductively connected to the first segment and the second segment. The first segment includes a first portion of the first bit line and a first portion of the second bit line. The second segment includes a second portion of the first bit line and a second portion of the second bit line. The twist segment includes a third portion of the first bit line and a third portion of the second bit line. The first and second portions of the first bit line and the second bit line each extends in a first lateral direction. The third portion of the first bit line is conductively connected to the first and second portions of the first bit line.

Abstract: A method is provided. The method includes preparing a mask blank, the mask blank including a substrate, a reflective layer disposed on the substrate for reflecting extreme ultraviolet light, and a light absorbing layer disposed on the reflective layer; providing a photomask by forming a plurality of pattern elements having a target critical dimension from the light absorbing layer, wherein the plurality of pattern elements include a correction target pattern element to be corrected, and the correction target pattern element has a critical dimension different from the target critical dimension; identifying a correction target area of the photomask in which the correction target pattern element is disposed; applying an etchant to the photomask; and irradiating a laser beam to the correction target area while the etchant is provided on the photomask.

Abstract: A method of forming a semiconductor structure includes forming a plurality of lower level conductive lines in a first dielectric layer. The plurality of lower level conductive lines includes a first lower level conductive line. The method further includes recessing portions of the first lower level conductive line below a top surface of the first dielectric layer to form a recess, forming a dielectric cap in the recess, depositing a second dielectric layer over the first dielectric layer. Forming a via opening exposes a portion of the second lower level conductive line. The method further includes forming an upper level conductive line and a via in the trench and in the via opening, respectively. The via couples the upper level conductive line to the second lower level conductive line, and the upper level conductive line overlaps with the dielectric cap.

Abstract: According to an aspect of the present disclosure, there is provided a pre-mold substrate including an electroconductive base member, which includes a first pre-mold groove formed in a bottom surface and a second pre-mold groove formed in a top surface and constitutes a circuit pattern; a first pre-mold resin disposed in the first pre-mold groove; and a second pre-mold resin disposed in the second pre-mold groove.

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Abstract: A display device with a connection carrier and a plurality of pixels, which are drivable via row lines and column lines, is specified. The row lines and the column lines are arranged on the connection carrier. At least one row line is interrupted at an imaginary crossing point with a column line on the connection carrier. A bridging component is arranged on the connection carrier, which bridges the row line at the imaginary crossing point in an electrically conductive manner.

Abstract: A display device includes a first electrode extending in a first direction; a second electrode extending in the first direction and spaced apart from, in a second direction, the first electrode; a light-emitting element having a shape extending in a direction and between the first and second electrodes such that the direction is parallel to the second direction; a first contact electrode having a shape extending in a third direction and having at least a portion on the first electrode; and a second contact electrode having a shape extending in the third direction, spaced apart from, in a fourth direction, the first contact electrode, and having at least a portion on the second electrode, the first contact electrode electrically contacts a side of the light-emitting element, and the second contact electrode electrically contacts another side of the light-emitting element.

Abstract: There is provided a structure of a nano memory system. The disclosed unit nano memory cell comprises a single isolated nanoparticle placed on the surface of a semiconductor substrate (301) and an adjacent nano-Schottky contact (303). The nanoparticle works as a storage site where the nano-Schottky contact (303) works as a source or a drain of electrons, in or out of the semiconductor substrate (301), at a relatively small voltage. The electric current through the nano-Schottky contact (303) can be turned on (reading 1) or off (reading 0) by charging or discharging the nanoparticle. Since the electric contact is made by a nano-Scottky contact (303) on the surface and the back contact of the substrate (301), and the charge is stored in a very small nanoparticle, this allows to attain the ultimate device down-scaling. This would also significantly increase the number of nano memory cells on a chip.

Abstract: A display device is provided. The display device comprises: a first substrate including a plurality of pixels; a second substrate opposite to the first substrate; and an optical path change layer disposed between the first and second substrates and including a first pattern portion and a second pattern portion, wherein the first pattern portion has a first refractive index and includes a blue colorant, and the second pattern portion has a second refractive index smaller than the first refractive index.

Abstract: A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

Abstract: A display apparatus including a display area including a first area having a first resolution and a second area having a second resolution that is lower than the first resolution and a non-display area comprises a conductive pattern arranged in the second area of the display area, a pixel electrode arranged in the second area, an opposite electrode facing the pixel electrode and contacting the conductive pattern, and a first electrode layer arranged in the non-display area and contacting the opposite electrode.

Abstract: Provided is an OLED display panel, the OLED display panel includes a touch layer, wherein the touch layer includes a via hole structure including: a first conductive layer, an interlayer insulating layer, and a second conductive layer that are sequentially arranged, wherein the interlayer insulating layer is provided with a via hole, the second conductive layer is overlapped with the first conductive layer by the via hole, and at least part of a surface, in contact with the second conductive layer, of the interlayer insulating layer is uneven; wherein the uneven surface has a roughness in a value range of 0.05d?r?0.19d, where r represents the roughness, and d represents a thickness of the interlayer insulating layer, the roughness of the uneven surface being a distance between a top of convex and a bottom of concave in the uneven surface.

Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

Abstract: A semiconductor device includes an anode, a cathode, a first functional layer between the anode and cathode, and a second functional layer between the first functional layer and the cathode. The first functional layer contains a first quantum dot having a first ligand, and the second functional layer contains a second quantum dot having a second ligand different from the first ligand. The second ligand is an aromatic compound having a sulfide bond and an ester bond.

Abstract: An electronic device comprises a semiconductor memory that includes: a memory cell; a protective layer disposed along a profile of the memory cell; and a buffer layer interposed between at least a portion of a sidewall of the memory cell and the protective layer, wherein the buffer layer and the protective layer include silicon nitride, and wherein a density of the protective layer is greater than a density of the buffer layer.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.

Abstract: A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.