Abstract: A power semiconductor device includes: a semiconductor body having a first surface and a mesa portion that includes a surface part of the first surface and a body region; at least two trenches extending from the first surface into the semiconductor body along a vertical direction, each trench including a trench electrode and trench insulator insulating the trench electrode from the semiconductor body, the mesa portion being laterally confined by the trenches in a first vertical cross-section along a first lateral direction; and a contact plug in contact with the body region. The contact plug and trench electrode of a first trench laterally overlap at least partially in the first vertical cross-section. A protection structure having a portion arranged within the first trench is arranged between the contact plug and trench electrode of the first trench. The protection structure may be an electrically insulation structure or a protective device structure.

Abstract: A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Abstract: An inertial sensor such as a MEMS accelerometer or gyroscope has a proof mass that is driven by a self-test signal, with the response of the proof mass to the self-test signal being used to determine whether the sensor is within specification. The self-test signal is provided as a non-periodic self-test pattern that does not correlate with noise such as environmental vibrations that are also experienced by the proof mass during the self-test procedure. The sense output signal corresponding to the proof mass is correlated with the non-periodic self-test signal, such that an output correlation value corresponds only to the proof mass response to the applied self-test signal.

Abstract: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 ?m or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Abstract: Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.

Abstract: A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

Abstract: In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.

Abstract: A display apparatus including a plurality of display modules each including a module substrate and a plurality of light emitting devices mounted on the module substrate, and a support substrate on which the display modules are disposed and including electrodes, in which the module substrate includes through-holes penetrating the module substrate and vias disposed in the through-holes, and the light emitting devices are electrically connected to the electrodes of the support substrate through the vias.

Abstract: Radiation hard semiconductor devices and packaging are disclosed. A semiconductor device assembly includes a substrate, a semiconductor die stack electrically coupled to the substrate, and an ionizing radiation shield disposed over a top die of the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC). The semiconductor device assembly further includes an encapsulant at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.

Abstract: Methods for cleaning a substrate are disclosed. The substrate comprises a dielectric surface and a metal surface. The methods comprise providing a cleaning agent to the reaction chamber.

Abstract: A package includes a first die, a second die, and an encapsulant. The first die includes a first capacitor. The second die includes a second capacitor. The second die is stacked on the first die. The first capacitor is spatially separated from the second capacitor. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

Abstract: In an embodiment a method for producing a lighting device includes providing a wafer assemblage having a semiconductor layer sequence arranged on a carrier substrate, separating the wafer assemblage into a plurality of first optoelectronic semiconductor chips, each comprising a section of the semiconductor layer sequence and of the carrier substrate, transferring at least some of the first optoelectronic semiconductor chips to a first auxiliary carrier, wherein the first auxiliary carrier has contact pads on a main surface, wherein the contact pads are surrounded and delimited in each case by a contour, and wherein each of the first optoelectronic semiconductor chips is arranged on a contact pad, cutting, on the first auxiliary carrier, to size the first optoelectronic semiconductor chips in order to adapt the first optoelectronic semiconductor chips to a predefined shape such that the each first optoelectronic semiconductor chip lies completely within the contour of an assigned contact pad, and transferring

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: A light emitting apparatus including a substrate, a plurality of light emitting diode devices disposed on the substrate, a light non-transmitting layer disposed on the substrate and having at least one of open regions, and a first conductive bonding layer disposed between the plurality of lighting emitting diode devices and the substrate and electrically contacting the plurality of light emitting diode devices, in which an upper surface of the first conductive bonding layer is placed above the light non-transmitting layer.

Abstract: A display apparatus including a display substrate, light emitting devices disposed on the display substrate, circuit electrodes disposed between the light emitting devices and the display substrate, and a transparent layer covering the light emitting devices and the circuit electrodes, in which at least one of the light emitting devices includes a first LED sub-unit configured to emit light having a first wavelength, a second LED sub-unit adjacent to the first LED sub-unit and configured to emit light having a second wavelength, a third LED sub-unit adjacent to the second LED sub-unit and configured to emit light having a third wavelength, and a substrate disposed on the third LED sub-unit, in which a difference in refractive indices between the transparent layer and air is less than a difference in refractive indices between the substrate and a semiconductor layer of the third LED sub-unit.

Abstract: A method for manufacturing a micromechanical structure in the structural layer of a wafer by forming a first gap and a second gap depositing and patterning a first etching mask and a second etching mask on a horizontal face of the structural layer, etching trenches through the structural layer in the first and second unprotected areas which are not protected by the first etching mask or the second etching mask, coating at least the sidewalls of the trenches with a protective layer and removing the second etching mask at least from a second opening in the first etching mask, so that a temporarily protected area is exposed, and etching away the structural layer in the exposed temporarily protected area.

Abstract: Disclosed are a method of manufacturing a thin film transistor, a thin film transistor, and an electronic device. The method of manufacturing a thin film transistor includes forming an oxide semiconductor layer, forming a gate electrode overlapped with at least a portion of the oxide semiconductor layer, and forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the forming of the oxide semiconductor layer includes preparing a precursor solution for an oxide semiconductor, and performing spray pyrolysis of the precursor solution for the oxide semiconductor to obtain a c-axis aligned crystalline oxide semiconductor.