Patents Examined by Victor Mandala
  • Patent number: 12255134
    Abstract: A method of forming a semiconductor structure includes forming a plurality of lower level conductive lines in a first dielectric layer. The plurality of lower level conductive lines includes a first lower level conductive line. The method further includes recessing portions of the first lower level conductive line below a top surface of the first dielectric layer to form a recess, forming a dielectric cap in the recess, depositing a second dielectric layer over the first dielectric layer. Forming a via opening exposes a portion of the second lower level conductive line. The method further includes forming an upper level conductive line and a via in the trench and in the via opening, respectively. The via couples the upper level conductive line to the second lower level conductive line, and the upper level conductive line overlaps with the dielectric cap.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: March 18, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Yi-Chun Huang, I-Chih Chen, Chun-Wei Kuo
  • Patent number: 12250856
    Abstract: A display apparatus including a display area including a first area having a first resolution and a second area having a second resolution that is lower than the first resolution and a non-display area comprises a conductive pattern arranged in the second area of the display area, a pixel electrode arranged in the second area, an opposite electrode facing the pixel electrode and contacting the conductive pattern, and a first electrode layer arranged in the non-display area and contacting the opposite electrode.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: March 11, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyunghoe Lee, Cheolgon Lee, Mukyung Jeon
  • Patent number: 12250863
    Abstract: Provided is an OLED display panel, the OLED display panel includes a touch layer, wherein the touch layer includes a via hole structure including: a first conductive layer, an interlayer insulating layer, and a second conductive layer that are sequentially arranged, wherein the interlayer insulating layer is provided with a via hole, the second conductive layer is overlapped with the first conductive layer by the via hole, and at least part of a surface, in contact with the second conductive layer, of the interlayer insulating layer is uneven; wherein the uneven surface has a roughness in a value range of 0.05d?r?0.19d, where r represents the roughness, and d represents a thickness of the interlayer insulating layer, the roughness of the uneven surface being a distance between a top of convex and a bottom of concave in the uneven surface.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 11, 2025
    Assignees: MIANYANG BOE OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Zhang, Daqing Sun, Wei Qiu, Fangliang Yan
  • Patent number: 12250889
    Abstract: A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: March 11, 2025
    Assignee: International Business Machines Corporation
    Inventors: Timothy Mathew Philip, Jin Ping Han, Kevin W. Brew, Ching-Tzu Chen, Injo Ok
  • Patent number: 12249544
    Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: March 11, 2025
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 12249571
    Abstract: According to an aspect of the present disclosure, there is provided a pre-mold substrate including an electroconductive base member, which includes a first pre-mold groove formed in a bottom surface and a second pre-mold groove formed in a top surface and constitutes a circuit pattern; a first pre-mold resin disposed in the first pre-mold groove; and a second pre-mold resin disposed in the second pre-mold groove.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: March 11, 2025
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Kwang Jae Yoo, Jong Hoe Ku, In Seob Bae
  • Patent number: 12249674
    Abstract: A display device includes a first electrode extending in a first direction; a second electrode extending in the first direction and spaced apart from, in a second direction, the first electrode; a light-emitting element having a shape extending in a direction and between the first and second electrodes such that the direction is parallel to the second direction; a first contact electrode having a shape extending in a third direction and having at least a portion on the first electrode; and a second contact electrode having a shape extending in the third direction, spaced apart from, in a fourth direction, the first contact electrode, and having at least a portion on the second electrode, the first contact electrode electrically contacts a side of the light-emitting element, and the second contact electrode electrically contacts another side of the light-emitting element.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 11, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun Deok Im, Jong Hyuk Kang, Hyun Min Cho
  • Patent number: 12249597
    Abstract: A display device with a connection carrier and a plurality of pixels, which are drivable via row lines and column lines, is specified. The row lines and the column lines are arranged on the connection carrier. At least one row line is interrupted at an imaginary crossing point with a column line on the connection carrier. A bridging component is arranged on the connection carrier, which bridges the row line at the imaginary crossing point in an electrically conductive manner.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: March 11, 2025
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Sebastian Wittmann, Thomas Schwarz
  • Patent number: 12250844
    Abstract: A display device is provided. The display device comprises: a first substrate including a plurality of pixels; a second substrate opposite to the first substrate; and an optical path change layer disposed between the first and second substrates and including a first pattern portion and a second pattern portion, wherein the first pattern portion has a first refractive index and includes a blue colorant, and the second pattern portion has a second refractive index smaller than the first refractive index.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 11, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keun Chan Oh, Sun Kyu Joo
  • Patent number: 12249638
    Abstract: There is provided a structure of a nano memory system. The disclosed unit nano memory cell comprises a single isolated nanoparticle placed on the surface of a semiconductor substrate (301) and an adjacent nano-Schottky contact (303). The nanoparticle works as a storage site where the nano-Schottky contact (303) works as a source or a drain of electrons, in or out of the semiconductor substrate (301), at a relatively small voltage. The electric current through the nano-Schottky contact (303) can be turned on (reading 1) or off (reading 0) by charging or discharging the nanoparticle. Since the electric contact is made by a nano-Scottky contact (303) on the surface and the back contact of the substrate (301), and the charge is stored in a very small nanoparticle, this allows to attain the ultimate device down-scaling. This would also significantly increase the number of nano memory cells on a chip.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 11, 2025
    Assignee: Khalifa University of Science and Technology
    Inventor: Moh'd Rezeq
  • Patent number: 12243914
    Abstract: A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Lee-Chung Lu, Ting-Wei Chiang, Li-Chun Tien
  • Patent number: 12243940
    Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
  • Patent number: 12245525
    Abstract: An electronic device comprises a semiconductor memory that includes: a memory cell; a protective layer disposed along a profile of the memory cell; and a buffer layer interposed between at least a portion of a sidewall of the memory cell and the protective layer, wherein the buffer layer and the protective layer include silicon nitride, and wherein a density of the protective layer is greater than a density of the buffer layer.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: March 4, 2025
    Assignee: SK hynix Inc.
    Inventors: So Young Yim, Jeong Soo Kim, Geun Hyeok Jang
  • Patent number: 12245446
    Abstract: A semiconductor device includes an anode, a cathode, a first functional layer between the anode and cathode, and a second functional layer between the first functional layer and the cathode. The first functional layer contains a first quantum dot having a first ligand, and the second functional layer contains a second quantum dot having a second ligand different from the first ligand. The second ligand is an aromatic compound having a sulfide bond and an ester bond.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 4, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayuki Sumida, Akira Shimazu, Takahiro Yajima, Tomona Yamaguchi
  • Patent number: 12243774
    Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 4, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Rui Li, Xiangjin Xie, Tae Hong Ha, Xianmin Tang, Lu Chen
  • Patent number: 12237239
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 25, 2025
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Young Khim, Ji Young Chung, Ju Hoon Yoon, Kwang Woong Ahn, Ho Jeong Lim, Tae Yong Lee, Jae Min Bae
  • Patent number: 12237381
    Abstract: A power semiconductor device includes: a semiconductor body having a first surface and a mesa portion that includes a surface part of the first surface and a body region; at least two trenches extending from the first surface into the semiconductor body along a vertical direction, each trench including a trench electrode and trench insulator insulating the trench electrode from the semiconductor body, the mesa portion being laterally confined by the trenches in a first vertical cross-section along a first lateral direction; and a contact plug in contact with the body region. The contact plug and trench electrode of a first trench laterally overlap at least partially in the first vertical cross-section. A protection structure having a portion arranged within the first trench is arranged between the contact plug and trench electrode of the first trench. The protection structure may be an electrically insulation structure or a protective device structure.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: February 25, 2025
    Assignee: Infineon Technologies AG
    Inventor: Alim Karmous
  • Patent number: 12237317
    Abstract: A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: February 25, 2025
    Assignee: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Junpeng Shi, Chen-Ke Hsu, Chang-Chin Yu, Yanqiu Liao, Zhenduan Lin, Zhaowu Huang, Senpeng Huang
  • Patent number: 12230661
    Abstract: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 ?m or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.
    Type: Grant
    Filed: April 12, 2024
    Date of Patent: February 18, 2025
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Young Kim, No Sun Park, Yoon Joo Kim, Seung Jae Lee, Se Woong Cha, Sung Kyu Kim, Ju Hoon Yoon
  • Patent number: 12227409
    Abstract: An inertial sensor such as a MEMS accelerometer or gyroscope has a proof mass that is driven by a self-test signal, with the response of the proof mass to the self-test signal being used to determine whether the sensor is within specification. The self-test signal is provided as a non-periodic self-test pattern that does not correlate with noise such as environmental vibrations that are also experienced by the proof mass during the self-test procedure. The sense output signal corresponding to the proof mass is correlated with the non-periodic self-test signal, such that an output correlation value corresponds only to the proof mass response to the applied self-test signal.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: February 18, 2025
    Assignee: InvenSense, Inc.
    Inventor: Aurelio Pellegrini