Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

Abstract: In an embodiment a method for producing a lighting device includes providing a wafer assemblage having a semiconductor layer sequence arranged on a carrier substrate, separating the wafer assemblage into a plurality of first optoelectronic semiconductor chips, each comprising a section of the semiconductor layer sequence and of the carrier substrate, transferring at least some of the first optoelectronic semiconductor chips to a first auxiliary carrier, wherein the first auxiliary carrier has contact pads on a main surface, wherein the contact pads are surrounded and delimited in each case by a contour, and wherein each of the first optoelectronic semiconductor chips is arranged on a contact pad, cutting, on the first auxiliary carrier, to size the first optoelectronic semiconductor chips in order to adapt the first optoelectronic semiconductor chips to a predefined shape such that the each first optoelectronic semiconductor chip lies completely within the contour of an assigned contact pad, and transferring

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: A light emitting apparatus including a substrate, a plurality of light emitting diode devices disposed on the substrate, a light non-transmitting layer disposed on the substrate and having at least one of open regions, and a first conductive bonding layer disposed between the plurality of lighting emitting diode devices and the substrate and electrically contacting the plurality of light emitting diode devices, in which an upper surface of the first conductive bonding layer is placed above the light non-transmitting layer.

Abstract: A display apparatus including a display substrate, light emitting devices disposed on the display substrate, circuit electrodes disposed between the light emitting devices and the display substrate, and a transparent layer covering the light emitting devices and the circuit electrodes, in which at least one of the light emitting devices includes a first LED sub-unit configured to emit light having a first wavelength, a second LED sub-unit adjacent to the first LED sub-unit and configured to emit light having a second wavelength, a third LED sub-unit adjacent to the second LED sub-unit and configured to emit light having a third wavelength, and a substrate disposed on the third LED sub-unit, in which a difference in refractive indices between the transparent layer and air is less than a difference in refractive indices between the substrate and a semiconductor layer of the third LED sub-unit.

Abstract: A method for manufacturing a micromechanical structure in the structural layer of a wafer by forming a first gap and a second gap depositing and patterning a first etching mask and a second etching mask on a horizontal face of the structural layer, etching trenches through the structural layer in the first and second unprotected areas which are not protected by the first etching mask or the second etching mask, coating at least the sidewalls of the trenches with a protective layer and removing the second etching mask at least from a second opening in the first etching mask, so that a temporarily protected area is exposed, and etching away the structural layer in the exposed temporarily protected area.

Abstract: Disclosed are a method of manufacturing a thin film transistor, a thin film transistor, and an electronic device. The method of manufacturing a thin film transistor includes forming an oxide semiconductor layer, forming a gate electrode overlapped with at least a portion of the oxide semiconductor layer, and forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the forming of the oxide semiconductor layer includes preparing a precursor solution for an oxide semiconductor, and performing spray pyrolysis of the precursor solution for the oxide semiconductor to obtain a c-axis aligned crystalline oxide semiconductor.

Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

Abstract: A package structure is provided. The package structure includes a first package component, a second package component, and a lid structure. The first package component includes a plurality of integrated circuit dies and an underfill formed between the integrated circuit dies. The second package component includes a substrate, and the first package component is mounted on the substrate. The lid structure is disposed on the second package component and around the first package component, and the lid structure covers the integrated circuit dies and exposes the underfill.

Abstract: A display device includes a substrate, a first electrode and a second electrode which are spaced apart from each other in a second direction, light-emitting elements spaced apart from each other in the first direction, a first contact electrode electrically contacting the light-emitting elements, and a second contact electrode electrically contacting the light-emitting elements. The first contact electrode electrically contacts the first electrode through a first contact portion disposed on the first electrode, the second contact electrode electrically contacts the second electrode through a second contact portion disposed on the second electrode, the first contact portion is disposed on an end portion in the first direction of the first contact electrode, and the second contact portion is disposed on an end portion in the first direction of the second contact electrode.

Abstract: Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. The diode portion includes a lifetime control region including a lifetime killer. Both the transistor portion and the diode portion include a base region of a second conductivity type on a surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region.

Abstract: The present application provides a method of manufacturing a memory device.

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

Abstract: A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

Abstract: Disclosed is an organic light emitting display device which may improve reliability. The organic light emitting display device includes light emitting elements arranged in an active area, crack prevention layers arranged in a non-active area along the perimeter of the active area, and at least one crack detection line arranged between the active area and the crack prevention layers, and judges whether or not a crack is generated through an output resistance value from the at least one crack detection line and may thus raise yield.

Abstract: An organic light emitting display (OLED) device includes an organic light emitting diode having an anode and a cathode. The organic light emitting diode is configured to receive a reference voltage. A control transistor includes a first control electrode and a first semiconductor active layer. The control transistor is configured to receive a control signal. A driving transistor includes a second control electrode that is electrically connected to the control transistor, an input electrode that is configured to receive a power voltage, an output electrode that is electrically connected to the anode of the organic light emitting diode, and a second semiconductor active layer that includes a different material from that of the first semiconductor active layer. A shielding electrode is disposed on the second semiconductor active layer, overlapping the driving transistor, and configured to receive the power voltage.

Abstract: Various embodiments of the present disclosure are directed towards an apparatus comprising a semiconductor substrate. A conductive pillar is disposed in the semiconductor substrate. An isolation region is disposed in the semiconductor substrate and extends laterally around the conductive pillar. The isolation region is configured to electrically isolate the conductive pillar from a surrounding portion of the semiconductor substrate. An opening is disposed in the isolation region. A dielectric anchor is disposed in the isolation region. The dielectric anchor extends vertically through the semiconductor substrate along a side of the opening. The dielectric anchor anchors the conductive pillar to the semiconductor substrate.