Patents Examined by Victor Perry
  • Patent number: 12670429
    Abstract: A method, system, and computer program product for reducing the sampling cost of quantum error mitigation. A map of root errors (“shaded light cone”), where each root error includes a likelihood an error impacts a state of a target qubit(s), is generated by computing time-evolved commutators of local errors and an observable (e.g., energy) or an initial state on a portion of the quantum circuit. A prioritization scheme is then applied after using the generated map to tighten an upper bound on a systematic error of a quantum error mitigation computation to reduce an error rate of the state of a target qubit(s). For example, error channels defined by a noise model may be prioritized using the upper bound. Anti-noise may then be applied to mitigate the error channels in order of priority. In this manner, there is a reduction in overall execution time for quantum error mitigation techniques.
    Type: Grant
    Filed: December 11, 2023
    Date of Patent: June 30, 2026
    Assignee: International Business Machines Corporation
    Inventors: Andrew Eddins, Patrick Julian Tassilo Rall, Minh Tran
  • Patent number: 12657688
    Abstract: A method for detecting word line shorts in a memory device includes: determining a region of interest (ROI) region in a bright voltage contrast (BVC) image for contact through-holes (CTs) of word lines in the memory device, the CTs comprising first CTs in at least one first word line that is electronically charged and second CTs in at least one second word line that is not electronically charged, and the ROI region comprising the at least one first word line; determining coordinates of each CT in the ROI region; reviewing a grayscale value at a position of the coordinates of each CT in the ROI region to determine whether the CT is a defective CT; and displaying the defective CT in response to the defective CT being determined.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: June 16, 2026
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Wenqi Wang, Wenlong Li, Ban Wang, Jinxing Chen, Yanli Wang, Zongliang Huo
  • Patent number: 12647214
    Abstract: A method of a first terminal may comprise: transmitting first SCI to a second terminal and a third terminal; transmitting a first TB to the second terminal and the third terminal based on scheduling by the first SCI; receiving a HARQ feedback including NACK information for the first TB through a first PSFCH resource; determining whether NACK information for at least one terminal among the second terminal and the third terminal has been received, based on the HARQ feedback; and in response to determining that the NACK information has been received, retransmitting the first TB to the at least one terminal.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: June 2, 2026
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Seon Ae Kim
  • Patent number: 12632769
    Abstract: Aspects of the disclosure include sending inputs according to the Floquet codes to be processed by a quantum circuit and receiving data streams from the quantum circuit, in response to the inputs. The data streams are encoded into a predetermined number of bits according to a probability density function for noise. The data streams are classified into hard outcomes having likelihoods of correctness, the hard outcomes representing output of the quantum circuit.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: May 19, 2026
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nicolas Guillaume Delfosse, Marcus Palmer da Silva, Yue Wu
  • Patent number: 12586654
    Abstract: The disclosure provides a method for performing self-test on a memory. The method can include determining an operation mode of a memory built-in self-test (MBIST) unit based on status of the memory; in response to the operation mode being a startup mode, configuring the MBIST unit to perform a memory self-test of a first type; and in response to the operation mode being a runtime mode, configuring the MBIST unit to periodically perform a memory self-test of a second type.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: March 24, 2026
    Assignee: Black Sesame Technologies Inc.
    Inventors: Qideng Yu, Gengyuan Zhang, Wei Chen, Ying Zhou
  • Patent number: 12493813
    Abstract: Techniques for optimizing distillation tile layouts for distillation tiles in a magic state factory of a quantum computer and a scheduling of distilled magic state production (e.g., using temporally encoded lattice surgery based (TELS-based) magic state distillation) using said distillation tiles are disclosed. Customized designs for distillation tile layouts that reduce space-time costs when executing a given quantum algorithm are presented, wherein the designs may be customized based, at least in part, on a selected classical error-correcting code and distillation circuit, on a decision whether to perform parallelized TELS-based magic state distillation, etc. Production of distilled magic states may then be configured using a round robin scheduling design in order to minimize potential time in which a processing core of the quantum computer is waiting for another newly distilled magic state from the magic state factory to use for logical computation related to the given quantum algorithm being executed.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 9, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Prithviraj Prabhu
  • Patent number: 12393477
    Abstract: A control device according to an embodiment includes a first region including a CPU and a sequence signal generation circuit; and a second region including an abnormality detection circuit, a sequence signal detection circuit, a first register storing multiple methods of recovery from occurrence of abnormality, and a second register for use to select one method of recovery from the multiple methods of recovery, the second region being higher in reliability than the first region. The sequence signal generation circuit converts a first signal that specifies the one method of recovery into a sequence signal containing a second signal, which is a digital signal of a predetermined pattern, and the sequence signal detection circuit changes a set value of the second register upon receiving the second signal.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: August 19, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Michitomo Yamaguchi, Satoshi Kamiya, Hiroshi Ichikawa