Abstract: The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with having low penetrating dislocation density and low surface roughness, prevent worsening of surface and interface roughness during heat treatment of a device production process and so forth. A production method of a semiconductor substrate W, in which SiGe layers 2 and 3 are formed on an Si substrate 1, is comprised of a heat treatment step in which heat treatment is performed either during or after the formation of the SiGe layers by epitaxial growth, at a temperature that exceeds the temperature of the epitaxial growth, and a polishing step in which irregularities in the surface formed during the heat treatment are removed by polishing following formation of the SiGe layers.

Abstract: According to the invention, while performing plasma-enhanced chemical vapor deposition on a substrate by exposing the substrate in a vacuum to a flow of particles generated by a plasma, which particles react to form a passivation layer on the substrate, a grid is interposed between the plasma and the substrate, thereby reducing the flow of charged particles towards the substrate while conserving a flow of neutral particles. The grid is formed of metal wires that are crossed at a pitch that is less than two or three times the Debye length (?D) of the plasma used, at least at the beginning of deposition. The aging properties of semiconductor components made by such a method is thereby improved.

Abstract: Disclosed are a liquid crystal display device and a method for manufacturing the same, in which wirings connected between pads and an integrated circuit is protected from being corroded. A pixel array is formed on a display region of a substrate. A plurality of pads are formed on a non-display region of the substrate. An integrated circuit is formed on the non-display region of the substrate and connected to the pads to generate a signal for operating the pixel array. Conductive barrier layers separated from each of the pads are formed on peripheral portions of the pads connected to the integrated circuit. The conductive barrier layers have electric potential equivalent to that of each of the pads in accordance with internal connections of the integrated circuit. When bumps of the integrated circuit and the pads are attached to each other, the conductive barrier layers prevent the pads and the wirings connected to the pads from being corroded.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract: An excited surfactant species is created by generating plasma discharge in a surfactant precursor gas. A surfactant species typically includes at least one of iodine, led, thin, gallium, and indium. A surface of an integrated circuit substrate is exposed to the excited surfactant species to form a plasma-treated surface. A ruthenium thin film is deposited on the plasma-treated surface using a CVD technique.

Abstract: A memory cell, array and device include an active area formed in the substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Abstract: Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).

Abstract: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range.

Abstract: A method for fabricating a seed layer. A seed layer (126) is deposited over a barrier layer (124) using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: Processes for fabricating a semiconductor device are described herein. In one aspect of the invention, an exemplary process includes forming an interface layer overlying the device substrate, forming a silver layer overlying the interface layer, annealing the substrate to form an intermetallic layer between the silver layer and the interface layer, the silver layer is in intimate contact with the intermetallic layer, and forming a protection layer overlying the silver layer. Other interconnect structures and processes are also described.

Abstract: A method for fabricating a semiconductor device capable of preventing an electric short between lower electrodes caused by leaning lower electrodes, or lifted lower electrodes and of securing a sufficient capacitance of a capacitor by increasing an effective capacitor area. The method includes the steps of: preparing a semi-finished semiconductor substrate; forming a sacrificial layer on the semi-finished semiconductor substrate; patterning the sacrificial layer by using an island-type photoresist pattern, thereby obtaining at least one contact hole to expose portions of the semi-finished semiconductor substrate; and forming a conductive layer on the sacrificial layer.

Abstract: The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant impurities over a time period into the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period. The dopant impurities are activation annealed to form one or more doped regions extending below the surface of the semiconductor substrate. The ion energy may be varied continuously or in a stepwise manner over the time period, and may also be varied in a cyclical manner.

Abstract: A method of producing a buried-type multilayer interconnection structure is provided. The method comprises steps of: forming a hole portion in an insulating layer; forming a catalyst layer having average film thickness from 0.2 nm to 10 nm on a surface of the hole portion by a physical vapor deposition method; forming an electroless plating layer on the surface of the hole portion by an electroless plating method using the catalyst layer as a catalyst; and burying up the hole portion with an electrolytic plating layer by an electrolytic plating method using the electroless plating layer as a seed layer.

Abstract: Bottom electrodes of stacked capacitor cells are formed by lining a patterned hard mask with a conductive layer. The hard mask is formed by a layered stack. Subsequent to the formation of trenches within the hard mask, the top-most masking layer of the layer stack is laterally recessed. The bottom electrode layer is then deposited to line the trenches. Following this, the bottom electrode layer is removed from the top of the hardmask. Subsequently, the hard mask is removed. As a result, released and free-standing elements of the conductive layer are formed as bottom electrodes that include a hydrophobic contact area in the top part of the bottom electrodes.

Abstract: A method for forming a dual damascene interconnect structure provides an intermetal dielectric that includes a spin-on low-k dielectric material formed over a CVD low-k dielectric material. A via opening is formed by etching through the spin-on low-k dielectric material and the CVD low-k dielectric material and a plug material is introduced to fill the via opening. A highly selective trench etching operation etches a trench in the upper, spin-on low-k dielectric material and removes the plug material from the via without attacking the lower CVD low-k dielectric material to form the dual damascene opening which is then filled with a conductive interconnect material. The intermetal dielectric formed of multiple low-k dielectric layers provides advantageous electrical and mechanical properties.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.