Abstract: A reconfigurable built-in self test circuit for enabling the debugging of an embedded device. In one embodiment, the write data path from the built-in self test module to the embedded device includes a multiplexer which is controlled by a debug signal. When the debug signal is de-asserted, the multiplexer forwards the write data from the built-in self test module to the embedded device, thereby allowing the self test to proceed in the hard wired manner. When the debug signal is asserted, the multiplexer forwards external data from the user to the embedded device, thereby allowing the user to execute customized tests on the embedded device. A second multiplexer is similarly placed in the expected data path from the built-in self test module to the comparator to allow the user to provide external data for comparison with output data from the embedded device when the debug signal is asserted.

Abstract: An improved display system which includes a central processing unit (CPU) coupled to a display utilizing vertical blanking intervals. A frame buffer memory is coupled to the CPU for storing data representative of color indices for each display pixel. The frame buffer is further coupled to look-up tables (LUTs) for storing color values which are provided through digital/analog converters (DACs) to the display. The CPU updates the contents of the frame buffer and/or LUTs during the vertical blanking interval of the display. A "first half" status flag is provided to the CPU at the beginning of each vertical blanking interval. This status flag remains true until one half of the period has elapsed. A "too late" status flag is also provided at the initiation of the interval which remains low until the end of the vertical blanking interval.

Abstract: This invention features a new computer system architecture comprising a variable comparison of input data with programmable Template data. The system has the capability to provide an "almost" condition, which is a similarity match between a near or close actual data and the "exact" data stored in template memory. Different degree levels of "almost" are possible with the inventive system.

Abstract: A method for controlling memory access to a user area and an initial code area of a main memory of a chip card includes carrying out an internal release procedure with a data comparison of an initial code from the initial code area and a data word from a terminal; firmly coupling addresses of the main memory and of a control memory to each other; marking several storage locations of the main memory as the initial code area with one control bit at a time in the control memory; marking a first code deposited in the associated storage location of the first code area as activated or deactivated with one further control bit at a time in the control memory; generating an initial release signal in a release procedure only if a storage location is addressed by an activated initial code and if agreement with the data word entered by the terminal prevails; and preventing generation of the initial release signal if a deactivated code word is addressed and/or if the respective first code does not agree with the data word

Abstract: A data processing system which includes an address bus connected to k computer elements is supervised with the aid of an arrangement including a plurality of indication registers connected to the bus and to an error signal generator. The address bus is capable of transferring 2n>k binary addresses. The indication registers are each accessed by its address transferred through the bus and each register stores an indication if its address is also assigned one of the computer elements. The generator generates an error signal on the reception of an indication that an address being transferred through the bus is not assigned a computer element.

Abstract: A microprocessor that has two operating modes for generating memory location addresses includes a processor 20 connected to a read-only memory 21, a random access memory 22, and an I/O unit 23 through control 25, data 26 and address 27 buses. A remapper unit 24 is connected in the address bus between the processor 20 and the read only memory and the random access memory so that when it is enabled by a signal from the I/O unit it can selectively change addresses generated by the processor and thus redirect the control of the microprocessor.