Patents Examined by (Vikki) Hoa B. Trinh
  • Patent number: 10366951
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Patent number: 10367092
    Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Setsuko Wakimoto, Masanobu Iwaya
  • Patent number: 10332830
    Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 25, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Wei-Che Huang, Tzu-Hung Lin
  • Patent number: 10297528
    Abstract: A semiconductor module includes case that houses a semiconductor device therein and a fastener that is connected at one end thereof to the case. The fastener includes a first extending portion that is connected at one end hereof to the case and extends away from the case, and a second extending portion that is connected at one end thereof to the first extending portion and extends toward the case, where the second extending portion has a variable angle with respect to the first extending portion depending on an external force. The second extending portion has a through hole penetrating through the second extending portion from a front surface of the second extending portion to a back surface of the second extending portion; and a projection that is provided on the back surface of the second extending portion, the projection being positioned closer to the case than the through hole is.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideki Hayashi
  • Patent number: 10269668
    Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
  • Patent number: 10262941
    Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Jason Eugene Stephens, Tuhin Guha Neogi, Kai Sun, Deniz Elizabeth Civay, David Charles Pritchard, Andy Wei
  • Patent number: 10205072
    Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: February 12, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Naoyuki Urasaki, Kanako Yuasa
  • Patent number: 10157866
    Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10147673
    Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 4, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 10141281
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Patent number: 10132836
    Abstract: A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.
    Type: Grant
    Filed: May 9, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John Knickerbocker, Yang Liu, Maurice Mason, Lubomyr T. Romankiw
  • Patent number: 10128212
    Abstract: A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die and the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 10128209
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Lan-Lin Chao, Cheng-Tai Hsiao, Xin-Hua Huang, Hsun-Chung Kuang
  • Patent number: 10106683
    Abstract: A resin composite includes a maleimide resin powder and a resin having a glass transition point that is lower that the glass transition point of the maleimide resin. The resin having a glass transition point that is lower than that of the maleimide resin may be an epoxy resin. Then, the resin composite may be cured at the curing temperature of the epoxy resin. The maleimide resin powder is mixed in an amount ranging from 50 weight % to 80 weight % with respect to the epoxy resin.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 23, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuko Nakamata, Yuji Ichimura
  • Patent number: 10096756
    Abstract: A side view LED package for a backlight unit includes a package body having a cavity with an inclined inner sidewall, first and second lead frames arranged in the package body, the cavity of the package body exposing a portion of at least one of the first and second lead frames placed in a bottom of the cavity to outside, a light emitting diode chip mounted on the bottom of the cavity to be electrically connected to the first and second lead frames, and a transparent encapsulant arranged in the cavity surrounding the light emitting diode chip. The cavity has a depth larger than a mounting height of the light emitting diode chip and not exceeding six times of the mounting height. The height of the sidewall is shortened to improve beam angle characteristics of emission light, increase light quantity, and prevent a molding defect of the sidewall.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Wook Kim, Yoon Suk Han, Young Jae Song, Byung Man Kim, Jae Ky Roh, Seong Jae Hong
  • Patent number: 10090147
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 2, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Chun Yan, Xinyu Bao, Melitta Manyin Hon, Hua Chung, Schubert S. Chu
  • Patent number: 10068822
    Abstract: A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region; subsequently, disposing at least one die structure onto the active region of the substrate respectively; and then injecting a molding compound flowed into the gap region, to mold the flow hindering supporter and the die structure with the molding compound.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 10068798
    Abstract: There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a surface of the substrate that defines the recess, and forming a seed layer on the barrier layer. The method further includes at least one of etching the barrier layer and etching the seed layer. In the at least one of etching the barrier layer and etching the seed layer, the substrate is inclined with respect to an irradiation direction of ions while rotating the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 4, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroyuki Toshima, Tatsuo Hatano, Shinji Furukawa, Naoki Watanabe, Naoyuki Suzuki
  • Patent number: 10068861
    Abstract: Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 4, 2018
    Assignee: ChipMOS Technologies Inc.
    Inventor: Kun-Shu Chuang
  • Patent number: 10003018
    Abstract: Embodiments are described for annealing systems and related methods to process microelectronic workpieces using vertical multi-batch perpendicular magnetic annealing systems that allow for a side-by-side configuration of multiple annealing systems to satisfy reduced footprint requirements.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 19, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Saito Makoto, Noel O'Shaughnessy, Toru Ishii, David Hurley