Abstract: An apparatus and method is disclosed for updating a status register in an out of order execution pipeline. In one embodiment a dispatch unit in a floating point unit sets a MRI bit flag that indicates that an instruction is the most recently issued instruction. The dispatch unit resets the MRI bit flag for all other instructions. Each execution stage of the execution pipeline keeps track of the MRI bit flag information for the instruction. A writeback unit updates the status register after the execution of the instruction that has its MRI bit flag set. The writeback unit does not update the status register for instructions that have their MRI bit flag reset. This allows the instruction to be identified that is the most recent instruction to enter the dispatch unit.

Abstract: According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of stages associated with the instruction to be executed and the number of stages associated with the subsequent instruction is provided.

Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.

Abstract: A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based on a configuration of components specified for the baseboard of the computer system. The customization program provides a user interface having a repository of icons and a design page. The icons represent various components that may be connected, either directly or indirectly, to the baseboard. The design page is used for constructing a model representing the specified configuration of components. As a user drags icons onto the design page, the model is updated to reflect selection of the components corresponding to these icons. Further, the customization program creates a configuration file that identifies and describes each of the selected components.

Abstract: A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address. Typically the return stack is more accurate. However, if the return stack mispredicts, update logic sets an override flag associated with the return instruction in the BTAC. The next time the return instruction is encountered, if the override flag is set, branch control logic branches the microprocessor to the BTAC prediction. Otherwise, the microprocessor branches to the return stack prediction. If the BTAC mispredicts, then the update logic clears the override flag. In one embodiment, the return stack predicts in response to decode of the return instruction. In another embodiment, the return stack predicts in response to the BTAC predicting the return instruction is present in an instruction cache line. Another embodiment includes a second, BTAC-based return stack.

Abstract: A CPU executes program instructions which result in valid and invalid intermediate results. By selecting the desired intermediate results, a program is able to be successfully executed. Analysis of the intermediate results must avoid plausible wrong results. A programmable feature allows the instruction decoder to provide plural answers, including plausible wrong answers. Instruction output selection logic selects a predetermined buffer, and this permits further microprocessor operation with the correct intermediate result.

Abstract: A recording/reproducing apparatus for recording a received signal as digital data in a file format and for reproducing the digital data stored in the file format includes a memory controller which controls the recording made in a manner such that the digital data continuously received and stored in a buffer memory is stored in a storage unit at a writing speed which is higher than a speed at which the digital data is stored in the buffer memory. In a reproducing mode, the digital data is read from the storage unit into the buffer memory at a reading speed which is higher than a speed at which the digital data is outputted from the buffer memory to the outside.

Abstract: A method and system for changing the executable status of an operation following a branch misprediction. In one embodiment, a method may include predicting an execution path of a first conditional branch operation stored in an entry of a trace cache, and in response to predicting the execution path, if a first operation stored in the entry of the trace cache is not in the execution path according to the prediction, assigning to the first operation a non-executable status indicative that the first operation is not in the execution path. The method may further include detecting that the prediction is incorrect subsequent to assigning the non-executable status to the first operation and assigning an executable status to the first operation in response to detecting the incorrect prediction, where the executable status is indicative that the first operation is in the execution path.

Abstract: A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic. The processor also includes second decoder logic capable of decoding a plurality of encoded instructions comprising a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic. Finally, the processor includes decoder control logic configured to selectively control active operation of the first decoder logic and the second decoder logic. In operation, the decoder control logic operates such that when the first decoder logic is decoding an instruction then the second decoder logic is operated in a lower-power, inactive mode. Likewise, when the second decoder logic is decoding an instruction then the first decoder logic is operated in a lower-power, inactive mode.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. The performance indicators and counter values may be used as a mechanism for identifying cache hits and cache misses. Performance counters are incremented each time the instructions of routines of interest are executed and each time the instructions must be reloaded into the cache. From the values of these counters the cache hit-miss ratio may be determined. When the cache hit-miss ratio becomes less than a predetermined threshold, i.e. a greater number of cache misses than cache hits, the present invention may determine that a problem condition has occurred and initiate “chase tail” operations for avoiding overwriting of entries in the cache.

Abstract: A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.

Abstract: A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken/not-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken/not-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed.

Abstract: A processor and method of automatic instruction mode switching between N-bit and 2N-bit instructions by using parity bit check. The processor and method includes an instruction input device having a memory for storing a plurality of 2N-bit words, an instruction fetch device fetching a 2N-bit word from the memory, and a mode switch logic determining whether the 2N-bit word fetched by the instruction fetch device is two (N-P)-bit instructions or one 2(N-P)-bit instruction to accordingly switch the processor to corresponding N-bit or 2N-bit mode, wherein when the 2N-bit word fetched is even parity, the 2N-bit word is determined as two (N-P)-bit instructions if two N-bit words included in the 2N-bit word are on the even parity state, or determined as a 2(N-P)-bit instruction if the two N-bit words are on the odd parity state.