Patents Examined by Vincent Wall
  • Patent number: 11107761
    Abstract: A semiconductor device may include a first conductive plate, a plurality of semiconductor chips disposed on the first conductive plate, and a first external connection terminal connected to the first conductive plate. The plurality of semiconductor chips may include first, second, and third semiconductor chips. The second semiconductor chip may be located between the first semiconductor chip and the third semiconductor chip. A portion of the first conductive plate where the first external connection terminal is connected may be closest to the second semiconductor chip among the first, second, and third semiconductor chips. The first conductive plate may be provided with an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: August 31, 2021
    Assignee: DENSO CORPORATION
    Inventor: Takanori Kawashima
  • Patent number: 11101360
    Abstract: A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Wen-Hsing Hsieh, Wen-Yuan Chen, Jon-Hsu Ho, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11101400
    Abstract: Systems and methods for a focused field avalanche photodiode (APD) may include an absorbing layer, an anode, a cathode, an N-doped layer, a P-doped layer, and a multiplication region between the N-doped layer and the P-doped layer. Oxide interfaces are located at top and bottom surfaces of the anode, cathode, N-doped layer, P-doped layer, and multiplication region. The APD may absorb an optical signal in the absorbing layer to generate carriers, and direct them to a center of the cathode using doping profiles in the N-doped layer and the P-doped layer that vary in a direction perpendicular to the top and bottom surfaces. The doping profiles in the N-doped layer and the P-doped layer may have a peak concentration midway between the oxide interfaces, or the N-doped layer may have a peak concentration midway between the oxide interfaces while the P-doped layer may have a minimum concentration there.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: August 24, 2021
    Assignee: Luxtera LLC
    Inventors: Gianlorenzo Masini, Kam-Yan Hon, Subal Sahni, Attila Mekis
  • Patent number: 11081502
    Abstract: A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: August 3, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11079639
    Abstract: A liquid crystal display panel is disclosed and includes: a substrate, a plurality of data lines and gate lines disposed on the substrate, the data lines intersecting the gate lines to form a plurality of pixel units each including a metal pattern layer, a color resist, and a gate electrode light shielding structure; the metal pattern layer disposed on the substrate; the color resist covering the metal pattern layer; the gate electrode light shielding structure disposed on the gate lines to shield a gap between adjacent pixel units, an edge of the gate electrode light shielding structure located in the color resist and retracting away from the color resist to form a retraction portion reducing an extent of the color resist edge overlapping the light shielding structure edge to prevent a blocking wall of the protruding gate electrode light shielding structure from being excessively high and affecting later processes.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 3, 2021
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Wu Cao
  • Patent number: 11075169
    Abstract: A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Denzil S. Frost, Richard T. Housley, Jianming Zhou
  • Patent number: 11063163
    Abstract: An infrared detector and a method for manufacturing it are disclosed. The infrared photo-detector contains a photo absorber layer responsive to infrared light, a first barrier layer disposed on the absorber layer, wherein the first barrier layer substantially comprises AlSb, a second barrier layer disposed on the first barrier layer, wherein the second barrier layer substantially comprises AlxGa1-xSb and a contact layer disposed on the second barrier layer.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: July 13, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J. De Lyon, Rajesh D. Rajavel
  • Patent number: 11037943
    Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 15, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Muneyuki Imai, James Kai
  • Patent number: 11031550
    Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 8, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Simon Jeannot
  • Patent number: 11024505
    Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
  • Patent number: 11024778
    Abstract: The present disclosure relates to a large scale film containing quantum dots or a dye, a method of preparing the large scale film, including: forming quantum dots or a dye dispersed in a solvent in the form of fibers or beads; applying pressure to an adhesive film to make the fibers or the beads adhere thereto; and curing the adhesive film onto which the fibers or the beads have adhered, and fibers or beads of quantum dots or a dye which are prepared by electrospinning.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: June 1, 2021
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Ho Kyoon Chung, Hee Yeop Chae, Sung Min Cho, Deok Su Jo, Subin Jung, Bokyoung Kim, Dae Kyoung Kim, Seunghwan Lee
  • Patent number: 11011438
    Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Moo Soon Ko, Jeong-Soo Lee, Jung Hwa Kim
  • Patent number: 11011442
    Abstract: A power module will be provided which can suppress insulation performance deterioration caused by heat cycle to ensure insulation performance, by suppressing generation of bubbles and occurrence of detachments between silicone gel and an insulating substrate at a high or low temperature or at a high working voltage.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 18, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masaki Taya
  • Patent number: 11004762
    Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 11, 2021
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takayuki Oshima, Shinichirou Wada, Katsumi Ikegaya, Hiroshi Yoneda
  • Patent number: 10991794
    Abstract: The present specification discloses a semiconductor device and a method for manufacturing same.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Poren Tang
  • Patent number: 10985095
    Abstract: A vehicle power module for converting power includes a lead frame configured to receive power from outside or to output power to the outside and a substrate configured to be bonded with the lead frame. The substrate includes a pattern layer disposed to be electrically connected to the lead frame, a conductive layer disposed apart from the pattern layer and configured to be electrically grounded, and an insulating layer disposed between the conductive layer and the pattern layer to insulate the pattern layer from the conductive layer. The pattern layer further protrudes toward the lead frame than the insulating layer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 20, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Kyoung-Kook Hong, Youngseok Kim
  • Patent number: 10978614
    Abstract: A light-emitting device includes an emission structure, a current block layer on the emission structure, a reflective layer on the current block layer, a protection layer that covers the reflective layer, and an electrode layer on the protection layer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-in Yang, Dong-hyuk Joo, Jin-ha Kim, Joon-woo Jeon, Jung-hee Kwak
  • Patent number: 10971438
    Abstract: A chip-on film and a display device including the same are disclosed. The chip-on film includes a first base film, a second base film positioned on the first base film, a film pad portion positioned on at least one side of the second base film and exposed to the outside of the first base film, and a coating layer positioned on one surface of the first base film.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 6, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jihun Song, Minseok Kim
  • Patent number: 10971377
    Abstract: A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: April 6, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenichi Shimamoto
  • Patent number: 10961118
    Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. In some embodiments, a ventilation trench and an isolation trench are concurrently within a capping substrate. The isolation trench isolates a silicon region and has a height substantially equal to a height of the ventilation trench. A sealing structure is formed within the ventilation trench and the isolation trench, the sealing structure filing the isolation trench and defining a vent within the ventilation trench. A device substrate is provided and bonded to the capping substrate at a first gas pressure and hermetically sealing a first cavity associated with a first MEMS device and a second cavity associated with a second MEMS device. The capping substrate is thinned to open the vent to adjust a gas pressure of the second cavity.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chia Lee, Chin-Min Lin, Cheng San Chou, Hsiang-Fu Chen, Wen-Chuan Tai, Ching-Kai Shen, Hua-Shu Ivan Wu, Fan Hu