Patents Examined by Vincent Wall
  • Patent number: 11456387
    Abstract: The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 27, 2022
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yuanjie Lv, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Shixiong Liang, Zhihong Feng
  • Patent number: 11450689
    Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: September 20, 2022
    Assignee: STMicroelectronics SA
    Inventors: Thomas Bedecarrats, Philippe Galy
  • Patent number: 11444156
    Abstract: Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 13, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hayato Okamoto, Ze Chen
  • Patent number: 11444167
    Abstract: A method of manufacturing a trench type semiconductor device includes the following steps. First, an epitaxial layer is formed on a substrate, then a trench is formed in the epitaxial layer, and a gate structure is formed in the trench. The gate structure includes an upper gate and a lower gate, and an intermediate insulating portion, and the intermediate insulating portion is located in and above the upper gate.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: September 13, 2022
    Assignee: Advanced Power Electronics Corp.
    Inventor: Jau-Yan Lin
  • Patent number: 11430742
    Abstract: An electronic device module includes a substrate, at least one first component and at least one second component disposed on one surface of the substrate, a second sealing portion having the at least one second component embedded therein, and disposed on the substrate, and a first sealing portion disposed outside of the second sealing portion, at least a portion of the first sealing portion being disposed between the at least one first component and the substrate.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 30, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong In Ryu, Suk Youn Hong, Gi Su Chi, Seung Hyun Hong, Ki Chan Kim
  • Patent number: 11430895
    Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Guangyu Huang, Haitao Liu, Akira Goda
  • Patent number: 11430817
    Abstract: A novel semiconductor device in which a metal film containing copper (Cu) is used for a wiring, a signal line, or the like in a transistor including an oxide semiconductor film is provided. The semiconductor device includes an oxide semiconductor film having conductivity on an insulating surface and a conductive film in contact with the oxide semiconductor film having conductivity. The conductive film includes a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti).
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: August 30, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Yukinori Shima, Masami Jintyou, Takashi Hamochi, Satoshi Higano, Yasuharu Hosaka, Toshimitsu Obonai
  • Patent number: 11430967
    Abstract: A display device includes a reflective electrode including a first region and a second region inclined relative to the first region, a lower electrode on the first region of the reflective electrode, a bank insulating layer covering an edge of the lower electrode, the bank insulating layer extending onto the second region of the reflective electrode, an upper electrode on a portion of the lower electrode exposed by the bank insulating layer, the upper electrode extending onto the bank insulating layer, and a light-emitting layer between the lower electrode and the upper electrode. The light-emitting layer extends between the bank insulating layer and the upper electrode. An optical path between the second region of the reflective electrode and the upper electrode is the same as an optical path between the first region of the reflective electrode and the upper electrode.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 30, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Kyung-Eon Lee
  • Patent number: 11424322
    Abstract: A semiconductor device may include: a gallium oxide substrate including a first side surface constituted of a (100) plane, a second side surface constituted of a plane other than the (100) plane, and an upper surface; and an electrode in contact with the upper surface, in which the gallium oxide substrate may include: a diode interface constituted of a pn interface or a Schottky interface; and an n-type drift region connected to the electrode via the diode interface, and a shortest distance between the first side surface and the diode interface is shorter than a shortest distance between the second side surface and the diode interface.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: August 23, 2022
    Assignees: DENSO CORPORATION, NATIONAL UNIVERSITY CORPORATION KYOTO INSTITUTE OF TECHNOLOGY
    Inventors: Tatsuji Nagaoka, Hiroyuki Nishinaka, Masahiro Yoshimoto
  • Patent number: 11424291
    Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Denzil S. Frost, Tuman Earl Allen, III
  • Patent number: 11417772
    Abstract: A semiconductor device includes a substrate, an oxide semiconductor film on the substrate, a first gate structure on the oxide semiconductor film and a contact that is in contact with the oxide semiconductor film, the contact being disposed on a boundary surface with the oxide semiconductor film, and including a metal oxide film that includes a transition metal.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Hee Cho, Woo Bin Song, Hyun Mog Park, Min Woo Song
  • Patent number: 11417779
    Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: August 16, 2022
    Assignee: The 13th Research Institute of China Electronics Technology Group Corporation
    Inventors: Yuanjie Lv, Yuangang Wang, Xingye Zhou, Xin Tan, Xubo Song, Xuefeng Zou, Shixiong Liang, Zhihong Feng
  • Patent number: 11417769
    Abstract: Provided are a thin film transistor and method for manufacturing the same, array substrate, display panel and display device. The thin film transistor includes: a gate pattern, a gate insulating layer, an active layer pattern, a source pattern and a drain pattern sequentially stacked. At least one of a surface of the source pattern facing the gate insulating layer, a surface of the drain pattern facing the gate insulating layer, and a surface of the gate pattern facing the gate insulating layer is a target surface which can diffusely reflect lights entering the target surface, to prevent part of the lights from entering the active layer pattern. The display device solves the problem of volt-ampere characteristic curve of the active layer pattern being deflected and a normal operation of the thin film transistor being affected, thereby weakening the influence of lights on the normal operation of the thin film transistor.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 16, 2022
    Assignees: BOE Technology Group Co., LTD., Hefei Xinsheng Optoelectronics Technology Co., LTD
    Inventors: Binbin Cao, Chao Wang, Lin Sun
  • Patent number: 11410875
    Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 9, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hau Thanh Nguyen, Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Masamitsu Matsuura, Kengo Aoya, Mutsumi Masumoto
  • Patent number: 11404569
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a ferroelectric structure overlying a substrate. A pair of source/drain regions are disposed in the substrate. A gate dielectric layer overlies the substrate and is spaced laterally between the pair of source/drain regions. The ferroelectric structure overlies the gate dielectric layer. The ferroelectric structure includes a ferroelectric layer and a sidewall spacer structure, where the sidewall spacer structure continuously laterally wraps around the ferroelectric layer. The ferroelectric layer comprises a first metal oxide and the sidewall spacer structure comprises a second metal oxide different than the first metal oxide.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Han-Jong Chia
  • Patent number: 11387431
    Abstract: The disclosure provides a method of manufacturing an encapsulation layer and a display substrate. The method of manufacturing the encapsulation layer includes: forming a strippable layer on a first region of a substrate; forming an organic material layer on a second region of the substrate, the organic material layer comprising a portion covering the second region and an overflow portion exceeding the second region and at least partially covering the first region, wherein the first region and the second region are adjoined to each other; and stripping the strippable layer from the substrate to remove the overflow portion of the organic material layer and form an organic encapsulation layer.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 12, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lingzhi Qian, Ziyu Zhang
  • Patent number: 11387278
    Abstract: An electronic device includes a plurality of pixel electrodes, an active layer on the plurality of pixel electrodes, an opposed electrode on the active layer and covering an entirety of an upper surface of the active layer, and a first encapsulation film on the opposed electrode wherein the opposed electrode and the first encapsulation film have a common planar shapes.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chui Joon Heo, Ryuichi Satoh, Kyung Bae Park, Yeon-Hee Kim, Takkyun Ro, Takao Motoyama, Se Hyuck Park
  • Patent number: 11380710
    Abstract: To provide a semiconductor device capable of reducing a parasitic capacitance, securing high reliability, and suppressing an increase in manufacturing cost. A semiconductor device is provided which includes a substrate including an embedded insulation film and a semiconductor layer on the embedded insulation film and on which a semiconductor element is formed and a gate electrode on the semiconductor layer, in which the gate electrode includes a band-shaped first electrode portion that extends from a center portion of the semiconductor layer and beyond an end of the semiconductor layer along a first direction in a case where the substrate is viewed from above, and in a cross section in a case where the first electrode portion and the substrate are cut along the first direction, a film thickness of the end of the semiconductor layer is thicker than a film thickness of the center portion of the semiconductor layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 5, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuji Ibusuki, Daisaku Okamoto
  • Patent number: 11374057
    Abstract: A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Pin-Cheng Hsu, Mauricio Manfrini, Chung-Te Lin
  • Patent number: 11367819
    Abstract: A light-emitting device array according to an embodiment includes a plurality of light-emitting devices connected to each other, each of the light-emitting devices comprising a light-emitting structure comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a (1-1)th electrode connected to the exposed first conductive semiconductor layer; a (1-2)th electrode connected to the second conductive semiconductor layer; (2-1)th and (2-2)th electrodes connected to the (1-1)th and (1-2)th electrodes, respectively; a first bonding layer disposed between the (1-1)th electrode and the (2-1)th electrode; and a second bonding layer disposed between the (1-2)th electrode and the (2-2)th electrode wherein the (2-1)th electrode of the first light-emitting device and the (2-2)th electrode of the second light-emitting device are integrated, and the (2-2)th electrode of the first light-emitting device and the (2-1)th electrode of the second light-emitting device are integr
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: June 21, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventor: Woo Sik Lim