Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.

Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

Abstract: An object of the present disclosure is to suppress reduction of noise resistance and parasitic oscillation in a semiconductor device. A semiconductor device includes: a plurality of semiconductor chips parallelly connected to each other; a source electrode; a first source pattern connected to the source electrode; a source sensing terminal; and a second source pattern connected to the source sensing terminal, wherein a surface of each of the semiconductor chips is connected to the first source pattern, a surface of a reference chip is connected to the second source pattern, a surface of at least one non-reference chip as the semiconductor chip other than the reference chip is not connected to the second source pattern, and a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

Abstract: According to one embodiment, a semiconductor device includes a first insulating layer, a gate electrode layer provided on the first insulating layer, a second insulating layer provided on the gate electrode layer, an oxide semiconductor layer provided along the second insulating layer, the gate electrode layer and the first insulating layer, a gate insulating layer provided along the second insulating layer, the gate electrode layer and the first insulating layer, and surrounding a side surface of the oxide semiconductor layer, and a first hydrogen barrier film surrounding the oxide semiconductor layer and the gate insulating layer.

Abstract: A transistor with a high on-state current and a semiconductor device with high productivity are provided. A first insulator; a second insulator over the first insulator; a third insulator and a first conductor over the second insulator; a fourth insulator over the third insulator and the first conductor; a fifth insulator over the fourth insulator; a first oxide over the fifth insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide; a third conductor over the fourth oxide; a sixth insulator over the second conductor; a seventh insulator over the third conductor; an eighth insulator over the fifth insulator to the seventh insulator; a fifth oxide over the second oxide and positioned between the second conductor and the third conductor; a ninth insulator over the fifth oxide; and a fourth conductor over the ninth insulator are included.

Abstract: A display device, a display panel, and a manufacturing method thereof are proposed. The display panel includes a substrate, a first insulation layer, a first electrode layer, a pixel definition layer, a light-emitting function layer and a second electrode.

Abstract: We describe herein a gate controlled bipolar semiconductor device comprising a collector region of a first conductivity type, a drift region of a second conductivity type located over the collector region, a body region of a first conductivity type located over the drift region, a body region of a second conductivity type located over the drift region, at least one first contact region of a second conductivity type located above the body region and having a higher doping concentration compared to the body region, at least one second contact region of a first conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the body region, at least one active trench extending from a surface into the drift region, wherein the at least one first contact region adjoins at least one active trench so that, in use, a channel region is formed along said at least one active trench and within the body region, and at l

Abstract: An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.

Abstract: A transistor having a large S value or a semiconductor device performing calculation utilizing a transistor operation in a subthreshold region is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a gate electrode including a region overlapping with the oxide semiconductor layer with an insulating layer therebetween, and a first conductive layer including a region overlapping with the oxide semiconductor layer with a ferroelectric layer therebetween. In particular, the ferroelectric layer includes a crystal having a crystal structure exhibiting ferroelectricity.

Abstract: A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line that are formed on a first side of the channel region, away from the ferroelectric gate dielectric layer, and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes that are formed adjacent the ferroelectric gate dielectric layer on a second side, opposite the first side, of the channel region.

Abstract: Provided is a ferroelectric memory device having a dielectric layer vertically interleaved between a first conductive line and a second conductive line. A first ferroelectric portion is arranged along a sidewall of the first conductive line and a second ferroelectric portion is arranged along a sidewall of the second conductive line. A channel layer is arranged along sides of the dielectric layer, the first conductive line, and the second conductive line. A topmost surface of the first ferroelectric portion is vertically separated from a bottommost surface of the second ferroelectric portion by the channel layer.

Abstract: Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ?3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ?7 nm).

Abstract: An improved power MOSFET having a super junction structure is disclosed. The improved power MOSFET includes a plurality of unit cells UC, and each of the plurality of unit cells UC includes a column region PC1, a column region PC2, a pair of trenches TR formed between the column regions PC1 and PC2 in the X-direction and a pair of gate electrodes GE formed in the pair of trenches TR via gate insulating films (GI). The pair of trenches TR and the pair of gate-electrodes GE extend in Y-direction in a plan view. A plurality of column regions PC1 are formed so as to be spaced apart from one another along the Y-direction, and a width(L1) of the column region PC1 in the Y direction is wider than a width(L2) of the column region PC1 in the X direction.

Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

Abstract: Provided is field-effect transistor structure including: a substrate including therein at least one 1st doped region, a 2nd doped region on one side of the 1st doped region, and a 3rd doped region on another side of the 1st doped region; a 1st channel structure including therein a 4th doped region on the 2nd doped region in the substrate; and a 2nd channel structure, at a side of the 1st channel structure, including therein a 5th doped region on the 3rd doped region in the substrate, wherein the 4th, 2nd, 1st, 3rd and 5th doped regions form a sequentially connected passive device.

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, an n? type epitaxial layer extending upward from the buffer layer in one direction, and having a fin channel, a p type layer disposed on the buffer layer and surrounding the side and upper surfaces of the n? type epitaxial layer, a gate insulating layer on the p type layer, and a gate electrode on the gate insulating layer.

Abstract: A display device, a display panel, and a manufacturing method thereof are proposed. The display panel includes a substrate, a first insulation layer, a first electrode layer, a pixel definition layer, a light-emitting function layer and a second electrode.

Abstract: A semiconductor structure includes, from bottom to top or from top to bottom, a gate electrode, a ferroelectric dielectric layer, a metal-rich metal oxide layer, a dielectric metal nitride layer, and a metal oxide semiconductor layer. A ferroelectric field effect transistor may be provided by forming a source region and a drain region on the metal oxide semiconductor layer. The metal-rich metal oxide layer and the dielectric metal nitride layer homogenize and stabilize the interface between the ferroelectric dielectric layer and the metal oxide semiconductor layer, and reduce excess oxygen atoms at the interface, thereby improving switching characteristics of the ferroelectric field effect transistor.

Abstract: A multilayered magnetic free layer structure is provided that includes a first magnetic free layer and a second magnetic free layer separated by a non-magnetic layer in which the second magnetic free layer has a lower perpendicular magnetic anisotropy field, Hk, as compared with the first magnetic free layer. The multilayered magnetic free layer structure of the present application substantially reduces the switching current needed to reorient the magnetization of the two magnetic free layers. The lower Hk value of the second magnetic free layer as compared to the first magnetic free layer improves the switching speed of the second magnetic free layer and thus reduces, and even eliminates, write errors.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.