Abstract: An optoelectronic semiconductor element includes a semiconductor chip for generating electromagnetic radiation. The chip includes: a radiation decoupling surface through which first electromagnetic radiation is emitted in a first wavelength range during operation and a conversion layer which is disposed directly on the radiation decoupling surface of the semiconductor chip. The conversion layer completely covers the radiation decoupling surface and has a main surface which is opposite the radiation decoupling surface. The conversion layer includes at least one luminescent substance which is designed to convert at least a portion the of first electromagnetic radiation into second electromagnetic radiation of a second wavelength range, wherein the second wavelength range is different from the first wavelength range. An optical feedback element is disposed directly on the main surface of the conversion layer and is designed to reflect at least a portion of the first and/or the second electromagnetic radiation.

Abstract: Power semiconductor packages are provided. In one example, the power semiconductor package includes one or more semiconductor die having a wide bandgap semiconductor material, a housing, and one or more electrical leads extending from the housing. The power semiconductor package further includes a creepage cutout. In one example, the power semiconductor package further includes a creepage feature.

Abstract: A memory device includes a stacked body of alternately arranged conductor-including layers and insulating films in the first direction and pillar bodies within the stacked body. Each pillar body includes first and second conductive pillars and an insulator pillar located between the first conductive pillar and the second conductive pillar. Each conductor-including layer includes a semiconductor member, an electrode film and a ferroelectric layer provided between the semiconductor member and the electrode film. The semiconductor members in the multiple conductor-including layers are separated from each other in the first direction.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and 0?y?1; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers. The aluminum content varies continuously throughout a thickness of at least one of the layers.

Abstract: A vertical gallium oxide transistor and a preparation method thereof. The method includes: annealing a gallium oxide material in an oxygen atmosphere at a range of temperature of 1000 to 1400° C. for 1 to 24 h so as to form a single crystal layer, a defective layer and an oxidized layer; removing the defective layer and the oxidized layer on a back of the gallium oxide material and the defective layer on a front of the gallium oxide material so as to obtain an initial sample; and preparing a heavily doped implanted layer on the oxidized layer, preparing a source electrode layer on the implanted layer, and preparing a trench perpendicular to a plane of the sample, and preparing a gate dielectric layer in the trench to fabricate a gate electrode and a drain electrode.

Abstract: In an embodiment an optoelectronic semiconductor device includes a carrier comprising a mounting side and an attachment side opposite the mounting side, a plurality of separate, metallic lead frame parts and a potting body mechanically holding together the lead frame parts, and a plurality of optoelectronic semiconductor chips mounted on the mounting side, wherein the lead frame parts project beyond the potting body at the mounting side, wherein at least some of the lead frame parts have a double-layered design so that the lead frame parts together form a support layer on the attachment side and a mounting layer on the mounting side, wherein the support layer is embedded in the potting body and the mounting layer extends at least partially onto the potting body.

Abstract: A semiconductor device may include a two-dimensional material layer including a two-dimensional semiconductor material having a polycrystalline structure; metallic nanoparticles partially on the two-dimensional material layer; a source electrode and a drain electrode respectively on both sides of the two-dimensional material layer; and a gate insulating layer and a gate electrode on the two-dimensional material layer between the source electrode and the drain electrode.

Abstract: A semiconductor device may include a two-dimensional material layer, one or more metal islands on the two-dimensional material layer, and a metal layer covering the metal islands on the two-dimensional material layer. The semiconductor device may be manufactured by a method including forming metal islands on a two-dimensional material layer using a redox method and forming a metal layer covering the metal islands on the two-dimensional material layer.

Abstract: A split gate trench device, including a substrate, an epitaxial layer having a trench, and a split gate structure, is provided. The epitaxial layer is formed on the substrate, and the split gate structure is disposed in the trench. The split gate structure includes a shielding gate, two top gates, a shielding oxide layer, a gate oxide layer, and an inter-gate oxide layer. Each of the two top gates has a shape that is wide at the top and narrow at the bottom.

Abstract: Provided is a semiconductor film having a corundum-type crystal structure composed of ?-Ga2O3 or an ?-Ga2O3 solid solution, and an X-ray rocking curve full width at half maximum of a (104) plane on at least one surface of the semiconductor film is 500 arcsec or less.

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.

Abstract: Provided are ferroelectric field effect transistor (FeFET) based memory devices. These devices include aluminum scandium nitride (AlScN) as a ferroelectric dielectric and 2D chalcogenide semiconductors as a semiconductor channel in the transistor. The disclosed materials, devices and fabrication processes involved are compatible with back end of the line (BEOL) processing of a silicon based microchip and also compatible with silicon microprocessor fabrication.

Abstract: A method of bonding substrates comprises depositing a fluorine-doped dielectric layer on a first substrate, exposing the fluorine-doped dielectric layer to a hydrogen-containing plasma, and directly bonding the fluorine-doped dielectric layer to a surface of a second substrate without the use of an intervening adhesive.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a bottom electrode layer over a substrate and forming a gate dielectric layer over the bottom electrode layer. The method for manufacturing the semiconductor structure also includes forming an active layer over the gate dielectric layer and forming an indium-containing feature vertically overlapping the bottom electrode layer. The method for manufacturing the semiconductor structure also includes forming a source/drain contact landing on the indium-containing feature.

Abstract: A MOSFET device includes a semiconductor substrate, serving as a drain region, and an epitaxial region disposed on an upper surface of the substrate. The MOSFET device includes multiple body regions formed in the epitaxial region, and multiple source regions. The body regions are disposed near an upper surface of the epitaxial region and spaced laterally from one another, and each of the source regions is disposed in a corresponding one of the body regions near an upper surface of the body region. The MOSFET device includes a gate structure having multiple planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region overlapping a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions, an upper surface of the trench gate being recessed below the upper surface of the epitaxial region.

Abstract: Provided is a semiconductor film having a corundum-type crystal structure composed of ?-Ga2O3 or an ?-Ga2O3 solid solution, and an impurity concentration and/or a heterogeneous phase amount differ between a front surface and a rear surface of the semiconductor film.

Abstract: A light-emitting element includes a first electrode, a second electrode, and a functional layer provided between the first electrode and the second electrode. Moreover, the light-emitting element includes: a third electrode provided to the functional layer through a first insulating film; a fourth electrode provided to the functional layer through a second insulating film; a stress applying unit made of a piezoelectric material, and applying stress to the functional layer in response to application of a voltage from the third electrode and the fourth electrode; a power supply connected to the third electrode and the fourth electrode; a detecting unit detecting a condition of the functional layer; a storage unit storing predetermined threshold value information; and a control unit controlling the power supply in accordance with a result of the detection obtained from the detecting unit and the predetermined threshold information stored in the storage unit.

Abstract: A semiconductor device includes a first conductive layer, a first insulating layer on the first conductive layer, an oxide semiconductor layer on the first insulating layer, and second and third conductive layers on the oxide semiconductive layer. The oxide semiconductor layer includes a first region, a second region in contact with the second conductive layer, a third region in contact with the third conductive layer, a first impurity region between the first region and the second region, and a second impurity region between the first region and the third region. The first impurity region is in contact with the second conductive layer. The second impurity region is in contact with the third conductive layer. An electrical conductivity of each of the first impurity region and the second impurity region is greater than an electrical conductivity of each of the second region and the third region.

Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.