Abstract: A computer program product for a system and method for destaging changed data from a shared cache castout in a shared data environment distributes castout ownership for a dataset among a plurality of systems having an update interest in the dataset. One system is designated as having castout ownership of the dataset in a primary state. All other systems having an update interest in the dataset hold castout ownership for the dataset in a backup state. When the primary owner relinquishes ownership, primary ownership is passed to one of the backup systems. A structure castout owner for the entire cache assumes the responsibility of castout out changed data for a dataset for which the primary castout owner has had a failure.

Abstract: In a data storage system having a direct access storage device (DASD) and a cache, a cache directory has two types of directory entries. A track directory entry TDE identifies up to one DASD track of data records currently stored in cache. All records stored in a DASD track can be stored in a cache storage space allocated for the DASD track identified by the TDE. A cylinder directory entry CDE identifies a number N of records from any track in a respective cylinder of tracks. N is a positive integer less than the total number of records storable in a DASD track. From one to all of the DASD tracks in one cylinder may be identified in a CDE. The cache data storage allocation corresponding to a CDE is the same as that allocated for a TDE. Each TDE is addressed by a DASD track address of a cylinder while a CDE is addressed using a pseudo track number corresponding to a servo track in the DASD. A record cast out control for the cache includes examining the number of records destaged.

Abstract: Within a data processing system, data transfer between a host device and a slave device is accomplished with only one write operation. The write operation performed by the host device, such as a central processing unit, is performed to an alias destination address, which is related to the destination address by an offset number. The data included within the write operation includes the source address of the data to be transferred. Such a data transfer operation could be utilized to transfer data to a display adapter for display of video related data on a display device.

Abstract: A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting.

Abstract: A system for extending the data capacity of a primary storage device in a computer which utilizes transparent data compression. The system utilizes a compressed memory even within the primary storage device along with a compression/decompression algorithm to extend the memory space. The system also includes a water line or limit within the primary storage device to ensure that memory space is always available.

Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect.

Abstract: A copy of data in a Host Computer is synchronized with a version located in Shared Memory in a Modular Development System (MDS). Whenever a change in one or more bits in a Line of Data in Shared Memory are detected, a MDS Line Dirty Flag is checked. If the Flag is not set, it is set and a message is sent to the Host Computer that the Line of Data is now dirty. Whenever the Host Computer receives this message for a Line of Data in its visible memory, it sends a request to the MDS to read that Line from Shared Memory and send it to the Host. Otherwise, a Host Line Dirty Flag is set. The Host Computer also sends a request to read a Line of Data when that Line of Data is scrolled onto a screen and the corresponding Host Line Dirty Flag is set.

Abstract: A computer system which corrects errors in a second level cache controller. The cache controller erroneously provides the cycle lock signal for the entire period of a writeback cycle followed by an I/O bus access, thus causing a deadlock if an I/O bus master needs access to the host bus at the same time. A circuit determines when the writeback cycle is occurring and masks the lock signal during the writeback operation, so that the long lock assertion is not present and the arbiters can properly control the access to the buses.

Abstract: A cache management system for dynamically switching between record caching and track caching. Statistics are collected within the cache management system to determine the type and amount of locality associated with a specific data set currently within the cache. Using these statistics, metrics of the actual hit ratio, whole-track hit ratio, and other-record-hit ratio are generated. The metrics are periodically reviewed for a given band, and the band is placed into one of three cache modes accordingly. The mode assignment determines what type of staging will be performed for data within the band in the event of a miss. The possible modes are: track mode for track-based staging, record mode for staging of a single record only, or uncached mode if no data is to be staged. If a band has been assigned to either record or track mode, the assignment is re-evaluated after for a predetermined number of I/O's (128).