Abstract: The present disclosure proposes: a distributor measuring box designed to be installed on a photovoltaic solar module, having a housing with a support section embodied to be supported on the solar module, an encompassing side wall, and a cover, and string line feedthroughs and/or string line connectors, and having a string current measuring module that includes a measuring component and an evaluation unit for measuring the string current in the distributor measuring box; a photovoltaic solar module having a plurality of solar cells, in which a distributor measuring box is mounted to the back of the solar module oriented away from the sun; and a photovoltaic system having a plurality of photovoltaic solar modules, having a plurality of string lines, having a generator junction box, and having at least one inverter for supplying the electrical power produced by the photovoltaic generator.

Abstract: An improved measurement system may include a source measure unit (SMU) capable of performing accurate low-level current measurements. Based on an SMU design that provides a controlled DC voltage source with precision current limiting and a controlled 0V (zero Volt) DC at the measurement terminal, an AC design may be implemented to establish the same (or very similar) conditions over a specified frequency range. Instead of controlling each digital-to-analog converter (DAC) at respective source terminals of the SMU as a respective DC output, each DAC may be controlled as a respective function generator with programmable frequency and continuously variable phase and amplitude. Off-the-shelf pipelined analog-to-digital converters (ADCs) may be used to monitor voltage, current and the voltage at the measurement terminal, and a Fourier transform may be used to obtain both the amplitude and relative phase measurements to be provided to respective control loops.

Abstract: Through-silicon vias (TSVs) are tested using a modified integrated circuit test probe array, an electron beam generation device, a beam direction control device and an electron beam detection device. The TSV extends through a silicon substrate with end portions exposed or accessible by contacts disposed on opposing upper and lower surfaces of the substrate. The test probe array includes a test probe that accesses the lower TSV end portion and applies an AC test signal. An electron beam is directed by the beam direction control device onto the upper substrate surface such that a beam portion reflected from the upper TSV end portion is captured by the electron beam detection device. Reflected beam data is then analyzed to verify the TSV is properly formed. Various scan patterns, different test signal frequencies and an optional resistive coating are used to enhance the TSV testing process.

Abstract: Operational and functional testing of the optical Physical Media Dependent Integrated Circuits (“PMD ICs”) is achieved by constructing a switchable on-chip load with similar or equivalent electrical characteristics of a targeted photonic device.

Abstract: A method and apparatus for docking a test head to a peripheral. A docking pin (150) is moved past a projection (803) in a catch (802). The docking pin is further moved until the catch rotates and the projection in the catch engages a notch or indentation (152, 156) in the docking pin. A piston (620) is moved on to the catch so that the catch is prevented from rotating. The piston is further moved so that the test head is docked to the peripheral.

Abstract: A device test method performed in a substrate test apparatus which includes a mounting table for mounting thereon a substrate on which a device having an electrode is formed, the mounting table being movable by a X-direction motor and a Y-direction motor, and a probe card arranged to face the mounting table. A measuring electrode is arranged to correspond to the electrode of the device, the probe card has a probe that is engageable with the measuring electrode, and the X-direction motor or Y-direction motor generates torque to keep the mounting table from moving when measuring an electrical characteristic of the device. In the device test method, after the probe is engaged with the measuring electrode, when measuring an electrical characteristic of the device, the maximum value of the torque generated by the X-direction motor or Y-direction motor is limited to a predetermined value or less.

Abstract: Apparatus for determining a location of a target, the apparatus comprising: first and second magnetic dipole beacons positioned at substantially a same spatial location having respectively first and second time dependent magnetic moments oriented in different directions that generate first and second magnetic fields having different time dependencies; at least one magnetic field sensor coil located at the location of the target that generates signals responsive to the first and second magnetic fields; and circuitry that receives the signals generated by the at least one sensor coil and processes the signals responsive to the different time dependencies of the magnetic fields to determine a location of the at least one sensor coil and thereby the target.

Abstract: An apparatus and a method for generating signals for ESD stress testing an electronic device are disclosed. In an embodiment the apparatus is configured to receive a source signal including a source pulse, delay the source pulse to generate a test signal including a test pulse with a pulse width in an ESD time range and generate an auxiliary signal including an auxiliary pulse with a pulse width in the ESD time range.

Abstract: Systems and methods for electronics systems are provided herein. An electronics system may comprise a heating circuit and a fault detection system. The heating circuit may include a heating element. The fault detection system may include a first resistor comprising a first resistance, a second resistor comprising a second resistance, the first resistance being equal to the second resistance, a voltage level detector, and a controllable switch connected in series with the first resistor and the second resistor, the controllable switch in electronic communication with the voltage level detector. A fault may be detected in response to the first voltage being greater than the second voltage.

Abstract: A testing fixture includes a base, a signal source, a workstation and a crimping mechanism. The base is provided with a sloping surface carrying the workstation and the crimping mechanism. The signal source is located on the base. The crimping mechanism applies testing signals transmitted by the signal source to the product to be tested. Additionally, the workstation performs an electrical function test on the product to be tested. The testing fixture can effectively perform an electrical function test on the product to be tested and has an integrated design of the base, the signal source, the workstation and the crimping mechanism, which facilitates management and maintenance. The base is also provided with a sloping surface carrying the workstation and the crimping mechanism to provide the testing fixture with an optimal testing angle, thereby facilitating operation and production.

Abstract: A system and method: receive an input signal and output digital samples representing the input signal; store the digital samples for at least one acquisition record of the input signal in an acquisition memory; detect a trigger event in the input signal and calculate a trigger address in the acquisition memory for a digital sample corresponding to the detected trigger event; perform digital signal processing on the digital samples of the acquisition memory to produce processed digital samples; detect an edge, representing a trigger, in the processed digital samples, and determine a measured trigger time; temporarily store the processed digital samples in a buffer memory at least until the edge detector detects the edge in the processed digital samples; determine a trigger correction value in response to the measured trigger time; determine a corrected beginning address of the buffer memory from the calculated trigger address and the trigger correction value; and read the processed digital data out from the bu

Abstract: Surge testing systems and methods to surge test a device under test (DUT) in which a host computer controls a pulse generator and an oscilloscope to automatically apply a high voltage pulse from the pulse generator through a current limiter to the DUT, the oscilloscope provides one or more current or voltage waveforms representing a voltage or current associated with the DUT and/or the pulse generator, and the host computer determines a pass or fail condition of the DUT for the applied high voltage pulse according to the waveform or waveforms.

Abstract: An inrush current recording module is installed in a power supply unit. The power supply unit has a front-stage power circuit and a back-stage power circuit. The front-stage power circuit includes a first ground terminal, and the back-stage power circuit includes a second ground terminal. The inrush current recording module includes a series circuit and a detection recording unit. The series circuit is formed by a capacitor and a resistor, and includes two ends thereof respectively connected to the first ground terminal and the second ground terminal. The detection recording unit detects the resistor to generate a voltage signal, compares the voltage signal with a voltage determination level, starts timing an inspection period when the voltage signal is greater than the voltage determination level, and records whether a current inrush current is harmful or harmless according to whether a power output signal is obtained within the inspection period.

Abstract: The embodiments described herein relate to an improved circuit technique for sensing current conducting in a power transistor coupled with an input power supply. The circuit includes a bi-directional current sensing circuit using current sensing transistor gate control. The circuit includes a forward current sensing transistor to sense current conducting in the power transistor during forward mode current of the circuit and a reverse boost current sensing transistor to sense current conducting during reverse current mode of the circuit. A level shifter is also provided with complementary outputs to either turn on the forward current sensing transistor or turn off the reverse boost current sensing transistor when the circuit is in forward current mode, or to turn off the forward current sensing transistor and turn on the reverse boost current sensing transistor when the circuit is in reverse current mode.

Abstract: Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.

Abstract: Universal holding apparatus for holding a device under test, DUT, said universal holding apparatus comprising: a base plate configured to mount at least two DUT holders for holding the device under test each DUT-holder having at least one pad, wherein the at least two DUT-holders are positionable on said base plate to clamp said device under test, DUT, between them, wherein the pad of at least one of said DUT-holders for holding the device under test, DUT, is slidable to adjust a clamping distance between the DUT-holders for engaging said device under test, DUT.

Abstract: Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

Abstract: A current sensing assembly includes a conductor having a first side, a second side opposite the first side, a third side, and a fourth side opposite the third side. The first side has a first notch formed therein and the second side has a second notch formed therein opposite the first notch. The current sensing assembly also includes a sensor assembly including a first magnetic sensor disposed in the first notch or proximate to the third side of the conductor between the first and second notches, and a second magnetic sensor disposed in the second notch or proximate to the fourth side of the conductor between the first and second notches.

Abstract: De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure. The distributed open dummy structure may include a first signal transmission line coupled to a left signal test pad and a second signal transmission line coupled to a right signal test pad, the first and second signal transmission lines having a smaller total length than a total length of signal transmission lines of the open dummy structure, and intrinsic transmission characteristics of the DUT can be derived from transmission parameters of the dummy test structures and the test structure.

Abstract: A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.