Abstract: An apparatus comprises floating-point processing circuitry to perform a floating-point operation with rounding to generate a floating-point result value; and tininess detection circuitry to detect a tininess status indicating whether an outcome of the floating-point operation is tiny. A tiny outcome corresponds to a non-zero number with a magnitude smaller than a minimum non-zero magnitude representable as a normal floating-point number in a floating-point format to be used for the floating-point result value. The tininess detection circuitry comprises hardware circuit logic configured to support both before rounding tininess detection and after rounding tininess detection for detecting the tininess status.

Abstract: A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which output a signed integer form fraction with a first bitwidth and a second bitwidth, along with a maximum exponent. The first bitwidth signed integer form fractions are summed by an adder tree using the first bitwidth to form a first sum, and when an excess leading 0 condition is detected, a second adder tree operative on the second bitwidth integer form fractions forms a second sum. The first sum or second sum, along with the maximum exponent, is converted into floating point result.

Abstract: Aspects of the invention include physical design-optimal Dadda architectures that scale with increasing operand size. Partial product arrays can be generated for two n-bit operands and columns in the partial product arrays can be shifted to a first row. The number of partial products in each column can be iteratively reduced across one or more stages until each column has at most two partial products. At each stage a maximum column height is determined and each column having a height greater than the maximum column height is reduced using half-adders and full-adders. Result bits of the half-adders and the full-adders are placed at the bottom of the current column and carry bits of the half-adders and the full-adders are placed at the bottom of the next column.

Abstract: Linear-feedback shift registers (LFSRs) for generating bounded random numbers (e.g., random numbers within a narrower range than those generated by a conventional LFSR of the same width) are described. In one embodiment, a bounded LFSR for generating an n-bit value comprises an m-bit LFSR with a range of 2m random numbers and an n?m bit LFSR with a range of 2n-m?1?k random numbers. The bounded LFSR further comprises logic to skip k values from a repeatable sequence of the n?m bit LFSR, which can, for example, be configured during the design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on the outputs of the m-bit LFSR and the n?m bit LFSR. In one embodiment, the bounded random number generated by the bounded LFSR is used as a random address in a row hammer mitigation system.

Abstract: The present description concerns a method of generation of a sequence of pseudo-random digital codes enabling to perform a permutation (3) of a first set of values (V) into a second set of values (Vp) based on said digital codes (CPos) representative of positions (j) of values (Vi) of the first set in the second set, including the steps of: generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number (W0) by application of a first function (24,26) from a seed number to the next seed number; applying a second function to each seed number of the chain to obtain each position code (CPos(j)), the second function including at least one permutation (PERM) followed by a bijection (BIJ).

Abstract: Configurable circuits include an input selection region, a computation region, a switching region, and an output region. The input selection region includes a set of input multiplexers and selects and routes input signals. The computation region includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection stage to generate a respective output signal. The switching region includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals. The output region includes a domino logic stage, having a set of transistors, coupled to output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables.

Abstract: A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.

Abstract: An information processing apparatus includes an annealing control unit, a spin interaction memory, a random number generation unit, and a spin state update unit and obtains a solution by using an Ising model. The annealing control unit controls an annealing step and a parameter of a temperature and a parameter of a self-action. The spin interaction memory stores the interaction coefficient of a spin. The random number generation unit generates a predetermined random number. The spin state update unit includes a spin buffer that stores values of a plurality of spins, an instantaneous magnetic field calculation unit that calculates instantaneous magnetic fields of the plurality of spins, a probability calculation unit that calculates update probabilities of the plurality of spins, and a spin state determination unit that updates the values of the spins based on the update probabilities and a random number.

Abstract: Folded integer multiplier (FIM) circuitry includes a multiplier configurable to perform multiplication and a first addition/subtraction unit and a second addition/subtraction unit both configurable to perform addition and subtraction. The FIM circuitry is configurable to determine each product of a plurality of products for a plurality of pairs of input values having a first number of bits by performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction, and performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits. The plurality of multiplication operations includes a first number of multiplication operations, and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations.

Abstract: This device comprises a fast sampler comprising: a truncated table associating with truncated random numbers rmsb coded on Nmsb bits, the only sample k for which, whatever the number rlsb belonging to the interval [0; 2Nr?Nmsb?1], the following condition is met: F(k?1)<(rmsb, rlsb)?F(k), where: (rmsb, rlsb) is the binary number coded on Nr bits and the Nmsb most significant bits of which are equal to the truncated random number rmsb and the (Nr?Nmsb) least significant bits of which are equal to the number rlsb, Nmsb is an integer number lower than Nr, a module for searching for a received truncated random number rmsb in the truncated table, and able to transmit the sample k, associated, by the truncated table, with the received truncated random number rmsb, by way of random number drawn according to the probability distribution ?.

Abstract: The disclosure provides a blockchain random number generating system and blockchain random number generating method. The blockchain random number generating system includes a smart contract. A second electronic device generates a second random number and a second hash value corresponding to the second random number, and transmits the second hash value to a first block of the smart contract. A first electronic device generates a first random number and a first hash value corresponding to the first random number, and transmits the first hash value to a second block of the smart contract. A fifth block of the smart contract receives a real-time transaction index, and generates a random seed according to the real-time transaction index, the first random number and the second random number and calculates a result of the smart contract in the fifth block according to the random seed.

Abstract: An apparatus comprises a noisy bias voltage generator circuit, a random seed generator circuit, and a random series generator circuit. The noisy bias voltage generator circuit may be configured to generate a plurality of noisy bias voltages in response to a plurality of input voltage signals and a first bias current signal. The random seed generator circuit may be configured to generate a random seed in response to the plurality of noisy bias voltages and a second bias current signal. The random series generator circuit may be configured to generate a series of true random bits in response to the random seed and a clock signal.