Abstract: An information processing apparatus includes an annealing control unit, a spin interaction memory, a random number generation unit, and a spin state update unit and obtains a solution by using an Ising model. The annealing control unit controls an annealing step and a parameter of a temperature and a parameter of a self-action. The spin interaction memory stores the interaction coefficient of a spin. The random number generation unit generates a predetermined random number. The spin state update unit includes a spin buffer that stores values of a plurality of spins, an instantaneous magnetic field calculation unit that calculates instantaneous magnetic fields of the plurality of spins, a probability calculation unit that calculates update probabilities of the plurality of spins, and a spin state determination unit that updates the values of the spins based on the update probabilities and a random number.

Abstract: Folded integer multiplier (FIM) circuitry includes a multiplier configurable to perform multiplication and a first addition/subtraction unit and a second addition/subtraction unit both configurable to perform addition and subtraction. The FIM circuitry is configurable to determine each product of a plurality of products for a plurality of pairs of input values having a first number of bits by performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction, and performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits. The plurality of multiplication operations includes a first number of multiplication operations, and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations.

Abstract: This device comprises a fast sampler comprising: a truncated table associating with truncated random numbers rmsb coded on Nmsb bits, the only sample k for which, whatever the number rlsb belonging to the interval [0; 2Nr?Nmsb?1], the following condition is met: F(k?1)<(rmsb, rlsb)?F(k), where: (rmsb, rlsb) is the binary number coded on Nr bits and the Nmsb most significant bits of which are equal to the truncated random number rmsb and the (Nr?Nmsb) least significant bits of which are equal to the number rlsb, Nmsb is an integer number lower than Nr, a module for searching for a received truncated random number rmsb in the truncated table, and able to transmit the sample k, associated, by the truncated table, with the received truncated random number rmsb, by way of random number drawn according to the probability distribution ?.

Abstract: The disclosure provides a blockchain random number generating system and blockchain random number generating method. The blockchain random number generating system includes a smart contract. A second electronic device generates a second random number and a second hash value corresponding to the second random number, and transmits the second hash value to a first block of the smart contract. A first electronic device generates a first random number and a first hash value corresponding to the first random number, and transmits the first hash value to a second block of the smart contract. A fifth block of the smart contract receives a real-time transaction index, and generates a random seed according to the real-time transaction index, the first random number and the second random number and calculates a result of the smart contract in the fifth block according to the random seed.

Abstract: An apparatus comprises a noisy bias voltage generator circuit, a random seed generator circuit, and a random series generator circuit. The noisy bias voltage generator circuit may be configured to generate a plurality of noisy bias voltages in response to a plurality of input voltage signals and a first bias current signal. The random seed generator circuit may be configured to generate a random seed in response to the plurality of noisy bias voltages and a second bias current signal. The random series generator circuit may be configured to generate a series of true random bits in response to the random seed and a clock signal.