Patents Examined by Volita Russell
  • Patent number: 6492264
    Abstract: A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered and a method for making a semiconductor device which has the steps of: forming selectively a given conductive type semiconductor region on a substrate; forming a Co—Si alloy layer on the entire surface of the semiconductor region; introducing Si into the entire surface or part of the Co—Si alloy layer; and conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: December 10, 2002
    Assignee: NEC Corporation
    Inventor: Noriaki Oda
  • Patent number: 6468838
    Abstract: The present invention provides a method for manufacturing a MOS transistor of an embedded memory on the surface of semiconductor wafer. The method of present invention is first to define a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to depose a dielectric layer, a undoped polysilicon layer, a silicide layer, a doped polysilicon layer, a protection layer and a photoresist layer sequentially. Next, a plurality of gate patterns on the memory array area is defined and the protection layer is etched to the surface of the doped polysilicon layer. Then a plurality of gate patterns on the periphery circuit region is defined in and the doped polysilicon layer, the silicide layer and the undoped polysilicon layer are etched to the surface of the dielectric layer so as to form gates of each MOS transistors in the memory array area and periphery circuit region. Finally a spacer and source and drain region are formed around each gate.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: October 22, 2002
    Assignee: United Microelectronic Corp.
    Inventors: Sun-Chieh Chien, Chien-Li Kuo
  • Patent number: 6468874
    Abstract: There is disclosed a method of manufacturing a capacitor in a semiconductor device. In order to solve the problems that it is difficult to secure an effective surface area and a misalignment between a capacitor plug and an underlying electrode occurs in a capacitor having a stack structure using a BST dielectric film, the present invention forms a contact layer and a diffusion prevention film within a first contact hole for plug in a plug shape, forms a second contact hole using an oxide film, deposits an underlying electrode material and then removes the oxide film to form an underlying electrode. Therefore, the present invention has outstanding advantages of increasing the effective surface area of an underlying electrode since a process of etching the underlying electrode which could not be etched easily can be omitted, and preventing diffusion of oxygen upon formation of a dielectric thin film since a direct contact of a metal/oxygen diffusion prevention film and the dielectric film can be avoided.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 22, 2002
    Assignee: Hyundai Electronic Industries Co., Ltd.
    Inventors: Yong Sik Yu, Kweon Hong
  • Patent number: 6444508
    Abstract: In a thin film transistor, a first insulating film on a silicon layer formed in an island on a substrate is smaller in thickness than the silicon layer so that the stepped island edges is gentle in slope to facilitate covering the island with a second insulating film. This reduces occurrence of gate leak considerably. Since the peripheral region of the stepped island is smaller in thickness than the central region above the channel, it is possible to minimize occurrence of gate electrode breakage. The silicon layer contains two or more inert gas atoms, and the atoms smaller in mass number (e.g., He) are contained in and near an interface with a silicon active layer while the atoms larger in mass number (e.g., Ar) than those smaller in mass number are contained in and near a second interface with a gate electrode.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: September 3, 2002
    Assignee: NEC Corporation
    Inventors: Hiroshi Tanabe, Katsuhisa Yuda, Hiroshi Okumura, Yoshinobu Sato
  • Patent number: 6413853
    Abstract: A method of forming a tungsten plug in a semiconductor device includes forming a contact hole in an insulating layer, forming a contiguous titanium layer in the contact hole and on the insulating layer, forming a titanium nitride layer on the titanium layer. forming a thin tungsten layer of about 50 angstroms or less on the titanium nitride layer by CVD (chemical vapor deposition), annealing the structure once the thin tungsten layer has been formed, and depositing additional tungsten by CVD to completely fill the contact hole. The titanium nitride layer can be formed by a discrete CVD process or as a result of the annealing process. Forming a thin tungsten layer by CVD before the contact hole is completely filled in with tungsten is used to stabilize the titanium layer. For instance, a small amount of fluorine from the source gas of the thin tungsten layer diffuses into the titanium layer.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: July 2, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Dai Jang, Jin-Ho Choi