Abstract: The invention relates to a non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal. In order to provide a fast and effective test structure to be used for fast reliability evaluation in monitoring of non-volatile memory elements on every wafer it is proposed according to the present invention that:—a group of said memory cells is connected in parallel,—the source terminals of the memory cells in the group are connected together and to a source line,—the drain terminals of the memory cells in the group are connected together and to a drain line,—the gate terminals of the memory cells in the group are connected together and to a gate line, and—said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.

Abstract: A resist pattern (51) is formed only on buried silicon oxide films (2) on the whole surface of an alignment mark area (11A) and a trench (10C). With the resist pattern (51), preetching is performed by dry etching, to remove the silicon oxide film (2) on the whole of a memory cell area (11B) and part of a peripheral circuit area (11C) by a predetermined thickness. After removing the resist pattern (51), a silicon oxide film (3) and a silicon nitride film (4) are removed by CMP polishing, to provide a height difference between the highest portion and the lowest portion of the silicon oxide film (2A) which serves as an alignment mark. Thus, a semiconductor device with trench isolation structure which achieves a highly accurate alignment without deterioration of device performance and a method for manufacturing the semiconductor device can be provided.

Abstract: A method of forming a field effect transistor includes, a) providing a silicon substrate having impurity doping of a first conductivity type; b) providing source and drain diffusion regions of a second conductivity type within the silicon substrate, the source region and the drain region being spaced from one another to define a channel region therebetween within the silicon substrate; c) providing a gate relative to the silicon substrate operatively adjacent the channel region; and d) providing respective ohmic electrical contacts to the source region and the drain region, the electrical contact to the source region comprising a substrate leaking junction, the electrical connection to the drain region not comprising a substrate leaking junction. A field effect transistor is also disclosed.

Abstract: Each byte of data in a high-density, electrically-erasable, programmable read-only-memory (EEPROM) cell array is selectively erased by forming a plurality of memory cells in each of a plurality of P-wells where the memory cells in each P-well are formed one byte wide by n rows in length. By forming the memory cells in each P-well to be one byte wide by n rows in length, each byte of data can be selectively erased by identifying the corresponding P-well and the row within the P-well.