Patents Examined by Vu David
  • Patent number: 6653179
    Abstract: For manufacturing a thin film semiconductor device, first conducted is a film-making step to make a non-single-crystalline semiconductor thin film (4) on an insulating substrate (1). Next conducted is an annealing step to irradiate laser light (50) for once heating and melting the non-single-crystalline semiconductor thin film (4) and then changing it into a polycrystal in its cooling process. Thereafter, a processing step is conducted to form thin film transistors in an integrated form, which includes the polycrystalline semiconductor thin film (4) as their active layer. For the purpose of ensuring uniform crystallization and enlargement of grain sizes, in the annealing step, by using a laser oscillator (51) including an excimer laser source, the laser light (50) having a pulse width not shorter than 50 ns is shaped by an optical system (53) to form a rectangular cross-sectional area whose sides are not shorter than 10 mm to sequentially irradiate the semiconductor thin film (4).
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: November 25, 2003
    Assignee: Sony Corporation
    Inventors: Masahiro Minegishi, Yasushi Shimogaichi, Makoto Takatoku, Hisao Hayashi
  • Patent number: 6287923
    Abstract: A silicon oxide layer is first formed on a silicon substrate. Then, a polysilicon layer is formed on a predetermined area of the silicon oxide layer and a first dielectric layer is formed on top of the polysilicon layer. Next, a second dielectric layer is uniformly covered on the surface of the silicon oxide layer, the polysilicon layer and the first dielectric layer. An etching back process is performed to completely remove the second dielectric layer positioned on top of the first dielectric layer and to make the second dielectric layer positioned around the periphery of the polysilicon layer and the first dielectric layer become spacers. An etching process is performed to completely remove the first dielectric layer between the spacers. An ion implantation process is performed to form two doping areas in the silicon substrate adjacent to the spacers which are respectively used as a source and a drain of the MOS transistor.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: September 11, 2001
    Inventor: Tzung-Han Lee