Abstract: A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.

Abstract: Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.